Unlock instant, AI-driven research and patent intelligence for your innovation.

Self-assembled sidewall spacer

A spacer, self-assembly technology used in electrical components, transistors, semiconductor/solid-state device manufacturing, etc., to solve problems such as modification, removal damage, and impractical device size

Active Publication Date: 2012-12-26
GLOBALFOUNDRIES INC
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, conventional methods of spacer formation involving deposition of a dielectric material such as silicon oxide or silicon nitride and anisotropic etching have become less practical as device dimensions continue to shrink
The anisotropic etch step used to form the spacers is also undesirable as it often alters, removes and / or damages various materials within the FET area

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Self-assembled sidewall spacer
  • Self-assembled sidewall spacer
  • Self-assembled sidewall spacer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] The present invention provides a spacer for protecting the topographical edge of a material or material stack in a nanostructure and a manufacturing method thereof. The present invention will now be described in detail with reference to the following discussion and the accompanying drawings of this application. Please note that the drawings of the present application are provided for explanatory purposes only and therefore are not drawn to scale.

[0020] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, process steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without the above specific details. In other instances, well-known structures or process steps are not described in order to avoid obscuring the invention.

[0021] It will b...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology.

Description

technical field [0001] The present invention relates to a nanostructure, and in particular to a semiconductor structure and a manufacturing method thereof. More specifically, the present invention relates to a nanostructure comprising at least one patterned region comprising at least one material and a method for fabricating such a structure using self-assembled polymer technology (self-assembled polymer technology). There is a topographic edge comprising sidewall spacers composed of polymeric block components of self-assembled polymers. Background technique [0002] The field-effect transistor (FET) is the basic building block of today's integrated circuits. Such transistors can be formed in conventional bulk substrates, such as silicon, or semiconductor-on-insulator (SOI) substrates. [0003] Currently, FETs are fabricated by depositing a gate electrode on a gate dielectric and substrate. In general, transistor fabrication processes perform photolithography and etching ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/49H01L21/266
CPCH01L29/7843H01L29/4983H01L21/28247H01L21/266H01L29/6659H01L29/66545H01L29/517H01L29/665
Inventor 布鲁斯·多丽丝卡尔·J·拉登斯
Owner GLOBALFOUNDRIES INC