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Static latch

A latching and static technology, applied in the latching field, can solve the problems of shortening the maintenance time of the frequency signal level and the like

Inactive Publication Date: 2011-03-23
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, when the frequency of the frequency signal increases, the period of the frequency signal and its level maintenance time are shortened, and the latch 1 cannot be used to generate the latch signal QB

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0031] refer to figure 2 , which shows a circuit diagram of the static latch according to the first embodiment of the present invention. The static latch 2 is controlled by the clock signal CLK and the inverted clock signal CLKB, and is used for storing the latch signal SQB on the output node NDO in response to the input signal SI. For example, the static latch 2 includes an inverter Inv for generating an inverted clock signal CLKB according to the clock signal CLK. The static latch 2 includes a clock-based driver 22 , a trigger circuit or flip-flop 24 and a weak latch unit 26 . The frequency driven driver 22 , the driving circuit 24 and the low driving force latch unit 26 are all coupled to the output node NDO.

[0032] The frequency-driven driver 22 includes nodes ND1, ND2, a driving unit 22a, and switches 22b and 22c. The driving unit 22a and the switch 22b are coupled to the node ND1. The driving unit 22a and the switch 22c are coupled to the node ND2.

[0033] The d...

no. 2 example

[0045] refer to Figure 4 , which shows a circuit diagram of the static latch according to the second embodiment of the present invention. Figure 4 The static latch 3 shown with the figure 2 The difference between the illustrated static latch 2 is that the static latch 3 further includes a trigger circuit 34', which includes a PMOS transistor for responding to the inverted frequency signal CLKB, and provides the switch 32b on the node ND1 together with the switch 32b. voltage to output NDO. In this way, because the trigger circuit 34' and the switch 32b are provided in parallel, the equivalent resistance between the node ND1 and the output terminal NDO can be effectively reduced. In this way, the time required for the latch signal SQB to be discharged to the voltage V1 can be effectively shortened.

no. 3 example

[0047] refer to Figure 5 , which shows a circuit diagram of a static latch according to a third embodiment of the present invention. Figure 5 The static latch 4 shown with the Figure 4 The difference of the static latch 3 shown is that the static latch 4 only includes a trigger circuit 44 having substantially the same circuit connection relationship and function as the trigger circuit 34 ′, and the trigger circuit 44 is used to respond to the anti-phase frequency signal CLKB, together with the switch 42b, provides the voltage on the node ND1 to the output terminal NDO. The trigger circuits corresponding to the trigger circuits 24 and 34 in the static latches 2 and 3 are omitted in the static latch 4 . Since the trigger circuit 44' and the switch 42b are connected in parallel, the equivalent resistance between the node ND1 and the output terminal NDO can be effectively reduced. In this way, the time required for the latch signal SQB to be powered up to the voltage V1 can ...

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PUM

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Abstract

The invention discloses a static latch which comprises a clock-based driver, an actuation circuit and a latch unit. The clock-based driver comprises a first node, a second node, a driving unit, a first switch and a second switch. The driving unit can respectively provide first voltage to the first node and provide second voltage to the second node by responding to first level and second level of an input signal. The first and the second switches can respectively provide the voltage on the first node to an output node by responding to a frequency signal and provide the voltage on the second node to the output node by responding to an inverted frequency signal. The actuation circuit can provide the voltage on the second node to the output node by responding to the frequency signal. The latch unit is used for maintaining the level of a latch signal when the frequency signal is disabled.

Description

technical field [0001] The present invention relates to a latch, and in particular to a static latch applied in memory. Background technique [0002] refer to figure 1 , which shows a circuit diagram according to a conventional latch. Traditionally, the latch 1 includes a node N, an inverter IV, a switch PG and a latch unit LL. The inverter IV is used for generating an inverted clock signal CKB in response to the clock signal CK. The switch PG receives the input signal SIN and provides the input signal SIN to the node N in response to the high signal level of the clock signal CK and the low signal level of the inverted clock signal CKB to establish the voltage signal SV. The latch unit LL includes a driving inverter DI for providing a latch signal QB in response to a voltage signal SV. The latch unit LL further includes a feedback inverter FBI for negatively feedbacking the latch signal QB to the node N, so as to maintain the voltage levels of the voltage signal SV and t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/037
Inventor 林永丰
Owner MACRONIX INT CO LTD
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