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Method of manufacturing semiconductor device

A semiconductor and gas purification technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as adverse effects and changes in device operation

Active Publication Date: 2015-05-20
WONIK IPS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, if Cu and SiH 4 contact and react with each other, the sheet resistance of the underlying interconnect may change, increasing resistance such as via resistance or interconnect resistance after the device is fully fabricated
Therefore, the operation of the device may be adversely affected
For example, the device may not operate at high speed

Method used

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  • Method of manufacturing semiconductor device
  • Method of manufacturing semiconductor device
  • Method of manufacturing semiconductor device

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Embodiment Construction

[0020] Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions of layers and regions are exaggerated for illustrative clarity. Like reference numbers refer to like elements throughout. It will also be understood that when a layer, film, region or panel is referred to as being "on" another, it can be directly on the other, or one or more intervening layers, films, regions or panels may also be present. . Further, it will be understood that when a layer, film, region or panel is referred to as being "under" another, it can be directly under another, and one or more intervening layers, films, ...

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PUM

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Abstract

Provided is a method of manufacturing a semiconductor device. In the method, after a thin liner is formed on a substrate on which a lower interconnection is formed, a silicon source is supplied to form a silicide layer under the liner by a reaction between the silicon source and the lower interconnection, and the silicide layer is nitrided and an etch stop layer is formed. Therefore, the lower interconnection is prevented from making contact with the silicon source, variations of the surface resistance of the lower interconnection can be prevented, and thus high-speed devices can be fabricated.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device by forming a silicide layer on an interconnect after forming a pad. Background technique [0002] Since recent semiconductor devices are highly integrated and operate at high speeds, fine and multilayer interconnects are used in semiconductor devices. In addition, in order to reduce RC signal delay, copper is used as an interconnection material, and a material having a low dielectric constant (k) is used as an insulating layer material. Furthermore, the difficulty in metal patterning caused by design rule reduction has led to the development of a damascene process in which metal etching and insulating layer gap filling are not performed in an interconnect formation process. [0003] In the damascene process, an etch stop layer and an interlayer insulating layer are formed on a substrate in which ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/314H01L21/318
CPCH01L21/02068H01L21/0217H01L21/02274H01L21/02301H01L21/76832H01L21/76834H01L21/76838H01L21/76849H01L21/76867H01L21/31H01L21/24H01L21/3185
Inventor 权永秀
Owner WONIK IPS CO LTD