Interface method of USB 1.1 bus and high-speed intelligent unified bus

A USB1.1 bus technology, which is applied in the interface field of USB1.1 bus and high-speed intelligent unified bus, can solve the problem of low speed, and achieve the effect of increasing reliability, reducing cost, and effective and reliable interconnection

Inactive Publication Date: 2011-04-20
NORTHWESTERN POLYTECHNICAL UNIV
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  • Abstract
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  • Application Information

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Problems solved by technology

[0004] In order to overcome the deficiency of the low speed when the existing USB1.1 bus is interconnected with other buses, the present invention provides an interface method between the USB1.1 bus and the high-speed intelligent unified bus, and realizes the analysis of the USB standard by designing the USB controller. Completely receive valid data on the USB1.1 bus, and realize high-speed transmission and reception of smart bus data through the high-speed transceiver SerDes using Fiber Channel; realize buffer storage of bidirectional data through the cache memory; realize clocks of different speed buses through the clock control module Switching can realize high-speed, reliable and effective transmission of two bus data

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  • Interface method of USB 1.1 bus and high-speed intelligent unified bus
  • Interface method of USB 1.1 bus and high-speed intelligent unified bus
  • Interface method of USB 1.1 bus and high-speed intelligent unified bus

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Embodiment Construction

[0020] refer to Figure 1~6 , to describe the present invention in detail.

[0021] This embodiment is an interface method between the USB1.1 bus and the smart bus, which realizes the high-speed optical fiber transmission of the USB1.1 device through the high-speed smart bus and the data reception of the high-speed optical fiber data based on the USB1.1 bus. The hardware structure of this embodiment includes a USB1.1 bus controller, an intelligent bus controller, a central bus arbitration controller and a high-speed mass memory.

[0022] In this embodiment, the scheduling and interface control of the two buses are mainly completed in the high-speed logic array FPGA, and the FPGA adopts the EP1C12 chip of the Cyclone series of Altera Corporation of the United States. The chip has a density of 12060 LE units, which can fully meet the needs of image processing algorithms and system logic control; 169 user-available I / O ports meet the system's multi-chip connection requirements f...

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Abstract

The invention discloses an interface method of a USB 1.1 bus and a high-speed intelligent unified bus, which is used for solving the technical problems of low rate for the existing USB1.1 bus to be interconnected with other buses. In the technical scheme, a USB controller is designed to analyze a USB standard so as to correctly and completely receive effective data on the USB1.1 bus; a high-speed transceiver SerDes receives and sends intelligent bus data at high speed by a fiber channel; a high-speed buffer storage stores bidirectional data in a buffering mode; and a clock control module realizes clock switch of buses with different rates so as to realize effectively and reliably high-speed transmission of two types of bus data.

Description

technical field [0001] The invention relates to a bus interface method, in particular to an interface method between a USB1.1 bus and a high-speed intelligent unified bus. Background technique [0002] Universal Serial Bus (USB) is a fast and flexible serial communication standard, which has the characteristics of high transmission rate, convenient use, low price, easy expansion, high reliability, and low power consumption; USB technology has evolved from USB1. 1 Developed to USB2.0, and then to the recent USB3.0, its transmission rate is getting higher and higher, and its application fields are more and more. Although the USB1.1 bus has been used less and less now, as a serial bus standard that was once commonly used, it still has a wide range of applications in real-time data acquisition, industrial field control and other fields. Therefore, there is still an urgent need to establish a data transmission interface between a USB1.1 bus with a maximum transfer rate of 12Mbps...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
Inventor 史忠科王闯贺莹
Owner NORTHWESTERN POLYTECHNICAL UNIV
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