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Phase detector for timing recovery loop

A timing recovery and timing error technology, applied in the field of signal processing, can solve the problems of high loss of lock rate, timing recovery phase detector can not work correctly, reduce system throughput, etc., to achieve the effect of reliable detection

Active Publication Date: 2011-05-11
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional timing recovery phase detectors that estimate timing information from equalized samples (such as the equalized digital signal 125) and hard decisions (such as the sign bit of the LLR value 127) may not work correctly in low SNR environments, resulting in unreliable Acceptably high loss-of-lock rate (LOLR), which reduces system throughput

Method used

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  • Phase detector for timing recovery loop
  • Phase detector for timing recovery loop
  • Phase detector for timing recovery loop

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Embodiment Construction

[0018] figure 2 is a block diagram of a read channel 200 for a hard disk drive using a "soft" phase detector 230, the subject of the present application. Similar to read channel 100 of FIG. 1 , read channel 200 receives an analog input signal 221 corresponding to data stored on the hard drive and generates a digital decoded output signal 229 representative of the data stored on the hard drive. . figure 2 Components 222-236 and signals 221-237 of FIG. 1 are similar to components 122-136 and signals 121-137 of FIG. 1, respectively. In addition to the phase detector 230, figure 2 Each of the elements of FIG. 1 works in a similar manner to the corresponding elements of FIG. 1 .

[0019] Unlike the phase detector 130 of FIG. 1 which generates an estimated timing error signal 131 based on the equalized digital signal 125 from the equalizer 124 and only the sign bit of the LLR value 127 from the soft detector 126, figure 2 A phase detector 230 generates an estimated timing error ...

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Abstract

In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates.

Description

technical field [0001] The subject matter of this application relates to signal processing, and more specifically to phase detection in timing recovery loops. Background technique [0002] FIG. 1 is a block diagram of a prior art read channel 100 for a hard disk drive. Read channel 100 receives an analog input signal 121 corresponding to data stored on the hard drive and generates a digital decoded output signal 129 representative of the data stored on the hard drive. [0003] Specifically, an analog-to-digital converter (ADC) 122 digitizes an analog input signal 121 to generate a digital input signal 123 . A digital finite impulse response (DFIR) filter equalizer 124 equalizes the digital input signal 123 to generate an equalized digital signal 125 . A soft detector 126 converts the equalized digital signal 125 into soft values, such as multi-bit log-likelihood ratio (LLR) values ​​127, where each LLR value has a hard decision sign bit and a multi-bit (e.g., 4-bit) confid...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/085
CPCG11B20/10009G11B20/10037G11B20/10055G11B20/10222G11B20/10296G11B2220/2516H03L7/07H03L7/0807H03L7/0812H03L7/091H03M1/1255H04L7/0054
Inventor 刘靖峰宋宏伟
Owner AVAGO TECH INT SALES PTE LTD