Successive approximation analog-digital converter and method thereof

Abstract

The invention discloses a successive approximation analog-digital converter, which comprises a comparator, a maximum significant digit analog-digital converter and a minimum significant digit analog-digital converter, wherein the comparator is provided with an inverting input end, a non-inverting input end and an output end and is used for outputting a comparison result; the maximum significant digit analog-digital converter is coupled at the non-inverting input end; and the minimum significant digit analog-digital converter is coupled at the inverting input end.

Description

technical field [0001] The present invention relates to a successive approximation analog to digital converter (successive approximation analog to digital converter, SAR ADC), in particular to a capacitor divided into two groups of maximum significant bit (MSB) and least significant bit (LSB), respectively coupled to a comparator The successive approximation analog-to-digital converter of the positive and negative terminals is suitable for high-resolution SARADC. Background technique [0002] figure 1 is a circuit schematic showing a conventional successive approximation analog-to-digital converter. exist figure 1 Among them, C*32 / 31 and all the capacitors on the right form the LSB capacitor bank, and all the capacitors on the left side of C*32 / 31 form the MSB capacitor bank. This is a 10-bit SAR ADC, and the MSB capacitor bank has 5 bits, and the LSB capacitor bank also has 5 bits. VIN is an analog input signal, VREF and VREF / 2 are reference voltages, cmpo is the output...

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Problems solved by technology

[0007] Based on the shortcomings of the above-mentioned traditional SAR ADC, it is necessary to use a more effective capacitor arrangement to solve the problem that the ratio of series capacitors in the traditional capacitor arrangement is not an integer multiple, so as to reduce the matching problem of capacitors

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