All-digital clock generation circuit and all-digital clock generation method

Abstract

The invention relates to an all-digital clock generation circuit and an all-digital clock generation method. In the invention, the input direction of the circuit comprises an input clock Fi, and the output direction comprises an output clock Fo; the input clock Fi is connected to an Nk frequency division unit, and the Nk frequency division unit is connected to a time mark generation unit; the reference input of the time mark generation unit comes from a reference clock Fr unit; the output clock Fo is connected to a phase comparison and clock recovery unit, and two inputs of the phase comparison and clock recovery unit respectively come from a time mark caching unit and a reference clock Frj unit; the reference input of the time mark caching unit comes from the reference clock Frj unit; and the time mark generation unit and the time mark caching unit are communicated through a time mark transmitting channel. The method realizes the frequency division and frequency multiplication processing of any positive rational number under the condition of only using an elementary digital logical circuit resource and provides synchronous clock outputs of various frequencies meeting the system application requirements without singly configuring a special module for a phase-locked loop.

Description

technical field [0001] The invention relates to a clock circuit, in particular to an all-digital clock generating circuit and an all-digital clock generating method. Background technique [0002] In the existing digital logic circuit design, it is often necessary to divide and multiply the input clock by any positive rational number. The relationship between the input clock Fi and the output clock Fo is as follows: M=Fo / ((Fi / N)), which can also be described as Fo / Fi=M / N, where M and N are both positive integers. When M>N, it is a frequency multiplication circuit. When M cannot be divided by N, it is a frequency multiplication circuit with fractions; when M<N, it is a frequency division circuit. When N cannot be divided by M, it is a frequency multiplication circuit with fractions. frequency division circuit. Existing digital circuits generally need to use a phase-locked loop to implement the above-mentioned frequency multiplication circuit and frequency division circ...

AI Technical Summary

Problems solved by technology

Adding a digital clock generation circuit with a dedicated phase-locked loop module costs more and is more complicated to implement

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