Anti-single event transient circuit

Abstract

The invention discloses an anti-single event transient circuit, which is realized in a way that: the input of a P network and an N network of a complementary metal oxide semiconductor (CMOS) logic gate is separated to form P input and N input which are the redundancy of each other; a pair of series-wound P-channel metal oxide semiconductor (PMOS) transistor and N-channel metal oxide semiconductor(NMOS) transistor is inserted between the P network and the N network; and constant bias voltages are applied to the gate ends of the inserted pair of PMOS transistor and NMOS transistor to form two output nodes P output and N output which are the redundancy of each other. The circuit provided by the invention has the advantages of anti-single event transient capacity, simple structure, low powerconsumption and the like, and is applied to a digital logic circuit, a sequential circuit and a memory circuit.

Description

technical field [0001] The present invention relates to a circuit, and more particularly to a circuit capable of resisting single-event transients. Background technique [0002] The radiation produced by high-energy protons or high-energy neutrons hitting the atomic nucleus and the heavy nuclear particles in cosmic rays can cause changes in the state of the circuit, such as transients in combinational logic and bit flips in memory-like units. This effect is the effect of a single particle The result is often called single event effect. Single event effects can be divided into single event upset (SEU), recoverable single event latch (SEL), single event transient (SET) and other single event soft errors, and also include single event burn (SEB), single event Hard errors such as particle gate breakdown (SEGR), unrecoverable single event latch-up (SEL), etc. [0003] figure 1 Shown is a traditional complementary CMOS logic gate structure, which is composed of P network 12, N ...

AI Technical Summary

Problems solved by technology

Three-mode redundancy plus majority voting can basically eliminate the effect of single-event transients, but it will bring extremely high overhead (>200%) in area and power consumption

Time redundancy is lower in area and power consumption than triple-mode redundancy, but there are still three or more latch unit redundancy and additional speed overhead

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