Realization of tile cache strategy in graphics processing unit (GPU) based on tile based rendering

Abstract

The invention discloses the realization of a tile cache strategy in a graphics processing unit (GPU) based on tile based rendering, which comprises a tile writing part and a tile reading part. When a tile is written, a tile number is taken as an index according to primitive tiling results, the tile is written into a cache space corresponding to the tile, a local counter is simultaneously maintained and 1 is added to the counter of the written tile, wherein a specific address of the cache space is obtained by calculation. When the tile is read, image information stored in the tile is sequentially read out according to values of the counters of each tile and transmitted to a plotting module.

Description

technical field [0001] The present invention mainly relates to the field of realization of block rendering in GPU chip design, and in particular refers to the realization of block storage strategy in GPU based on block rendering. Background technique [0002] Computer graphics rendering technology has long been an important direction of information technology research, especially in the past ten years, with the continuous improvement of computer performance, computer graphics applications have also extended from 2D to 3D, and the corresponding application range has become wider. It plays an important role in various aspects such as commerce, industry, entertainment, art, education, medical care, military, etc. The implementation architecture of graphics chips is also constantly innovating and developing. [0003] In the field of early GPU design, the fixed pipeline (Fixed Pipeline) design method was generally adopted. Its fixed process includes: geometric transformation, li...

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Problems solved by technology

Its fixed process includes: geometric transformation, lighting, clipping, rasterization, Z test, texture mapping, etc. In addition to providing sufficient integer and floating-point operations in the design, another important consideration is the bandwidth of the memory bank According to the research, in the rendering stage, the main factor affecting the running speed of the GPU is the bandwidth of the storage body, because in this process, it is necessary to frequently read external memory data such as texture, depth, and frame memory, and often a pixel needs to be read In order to reduce the impact of memory bandwidth, the method of increasing on-chip storage (Cache) is often adopted in this architecture to reduce the amount of access to external memory, but this method The power consumption of the chip is increased, and the degree of performance improvement is limited.

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