Realization of tile cache strategy in graphics processing unit (GPU) based on tile based rendering

A block rendering and block storage technology, applied in the field of block rendering, can solve the problems of limited performance improvement, increased chip power consumption, etc., and achieve the effects of excellent performance, time saving, and simple logic

Active Publication Date: 2011-06-15
CHANGSHA JINGJIA MICROELECTRONICS
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Its fixed process includes: geometric transformation, lighting, clipping, rasterization, Z test, texture mapping, etc. In addition to providing sufficient integer and floating-point operations in the design, another important consideration is the bandwidth of the memory bank According to the research, in the rendering stage, the main factor affecting the running speed of the GPU is the bandwidth of the storage body, because in this proces

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  • Realization of tile cache strategy in graphics processing unit (GPU) based on tile based rendering
  • Realization of tile cache strategy in graphics processing unit (GPU) based on tile based rendering

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[0009] Hereinafter, the present invention will be further described in detail with reference to the drawings and specific embodiments.

[0010] Such as figure 1 As shown, the implementation of the block storage strategy in the GPU based on block rendering of the present invention includes the determination of the maximum number of blocks contained in each block. In this implementation, the block storage space is set to a fixed size area, while setting the block size If the size is a fixed value, then the size of the drawing area is different, the number of blocks that can be stored in the storage area is different, and the number of primitives that can be stored in each block is different. According to the block number sent in by the graphic element, the number of blocks stored in the current block is taken from the local RAM (the counter that maintains each block inside). If the block is processed for the first time, then the number of blocks is 0 . According to the number of ...

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Abstract

The invention discloses the realization of a tile cache strategy in a graphics processing unit (GPU) based on tile based rendering, which comprises a tile writing part and a tile reading part. When a tile is written, a tile number is taken as an index according to primitive tiling results, the tile is written into a cache space corresponding to the tile, a local counter is simultaneously maintained and 1 is added to the counter of the written tile, wherein a specific address of the cache space is obtained by calculation. When the tile is read, image information stored in the tile is sequentially read out according to values of the counters of each tile and transmitted to a plotting module.

Description

technical field [0001] The present invention mainly relates to the field of realization of block rendering in GPU chip design, and in particular refers to the realization of block storage strategy in GPU based on block rendering. Background technique [0002] Computer graphics rendering technology has long been an important direction of information technology research, especially in the past ten years, with the continuous improvement of computer performance, computer graphics applications have also extended from 2D to 3D, and the corresponding application range has become wider. It plays an important role in various aspects such as commerce, industry, entertainment, art, education, medical care, military, etc. The implementation architecture of graphics chips is also constantly innovating and developing. [0003] In the field of early GPU design, the fixed pipeline (Fixed Pipeline) design method was generally adopted. Its fixed process includes: geometric transformation, li...

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Application Information

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IPC IPC(8): G06T1/60G06T11/20
Inventor 焦勇饶先宏陈怒兴
Owner CHANGSHA JINGJIA MICROELECTRONICS
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