Multiprocessor system and multiprocessor system interrupt control method

A technology of a multi-processor system and control method, applied in the direction of electrical digital data processing, instruments, etc., can solve the problem of reduced interrupt response ability, and achieve the effect of improving interrupt response ability

Inactive Publication Date: 2011-06-15
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] However, in previous interrupt control methods, the responsibility for interrupt handling was assigned to a specific processor
Therefore, when the response capability of the processor assigned the responsibility is

Method used

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  • Multiprocessor system and multiprocessor system interrupt control method

Examples

Experimental program
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Embodiment 1

[0070] figure 1 It is a block diagram showing the configuration of the multiprocessor system according to Embodiment 1 of the present invention.

[0071] figure 1 The multiprocessor system shown has: processors 101 , 102 , 103 and 104 ; shared bus 110 ; shared memory 120 ; interrupt generator 130 ; I / O devices 141 , 142 and 143 ;

[0072] The processors 101 , 102 , 103 and 104 are able to communicate with each other via the shared bus 110 . Also, the processors 101 , 102 , 103 and 104 can access the shared memory 120 via the shared bus 110 . Furthermore, the processors 101, 102, 103, and 104 include mask level registers 161, 162, 163, and 164, respectively.

[0073] The interrupt generator 130 has a factor and priority table 150 . Factor and priority table 150 has predefined interrupt priorities for I / O devices 141, 142, and 143, respectively.

[0074] And, the interrupt request of the I / O device 141 , 142 or 143 is notified to the interrupt generator 130 via the I / O in...

Embodiment 2

[0101] In the second embodiment, a multiprocessor system in which the allocation of interrupt-permitted processors can be appropriately changed in accordance with the respective interrupt priorities of the I / O devices 141 , 142 , and 143 will be described.

[0102] Figure 7 It is a block diagram showing the configuration of a multiprocessor system according to Embodiment 2 of the present invention. Figure 7 The multiprocessor system shown, with the example 1 of figure 1 Compared with the illustrated multiprocessor system, the difference lies in the configuration of the shared memory 720 , and the difference of the shared memory 720 is that a priority and number of processors table 700 is added. Also for figure 1 The same symbols are assigned to the same elements, and detailed description thereof will be omitted.

[0103] Figure 8 It is a diagram showing the relationship between the interrupt priority and the number of interrupt-permitted processors according to Embodi...

Embodiment 3

[0153] In Embodiment 3, an interrupt control method of such a multiprocessor system is described. On the basis of the interrupt control method of a multiprocessor system in Embodiment 2, the process of selecting and permitting interrupts from all processors is further set. The selection basis of the processor time, so as to achieve the optimization of the whole system.

[0154] In particular, in Embodiment 3, an interrupt control method for a multiprocessor system is described, that is, in an OS (Operating System: processing system) that controls multiple tasks on the multiprocessor system, each processor executes the The task priority of the task is used as a selection basis to effectively execute tasks with high task priority.

[0155] Figure 16 It is a block diagram showing the configuration of a multiprocessor system according to Embodiment 3 of the present invention. Figure 16 The multiprocessor system shown, with the example 2 of Figure 7 Compared with the illustra...

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Abstract

A multiprocessor system can improve the entire system processing efficiency while assuring an appropriate interrupt response based on an interrupt priority. The multiprocessor system includes: a plurality of processors each having a register; a plurality of I/O devices; and an interrupt generator. An interrupt control method includes: a setting step in which a corresponding processor sets an interrupt allowance degree in a register; a report step in which the interrupt generator which has caused a storage unit to store the interrupt priority indicating a priority for an interrupt from each of I/O devices receives an interrupt request from an I/O device and reports the interrupt request to a plurality of processors together with the interrupt priority of the I/O device; and an interrupt acceptance step in which the interrupt request is accepted by any one of the processors having the register in which a lower interrupt allowance degree is stored as compared to the interrupt priority.

Description

technical field [0001] The invention relates to a multiprocessor system and an interrupt control method of the multiprocessor system, in particular to a multiprocessor system for controlling interruption and an interrupt control method of the multiprocessor system. Background technique [0002] A typical multiprocessor system has: multiple processors capable of interrupt handling; a shared bus; shared memory, which the processors can access via the shared bus; and interrupt generators, which will perform input or output of data. The signal of the / O (Input / Output: input and output) device is notified to the processor as an interrupt signal. [0003] Here, the term "interruption" refers to causing another process to be performed while a certain continuous process is in progress. [0004] In a typical multiprocessor system, an interrupt occurs due to a signal from an I / O device, and responsibility for interrupt processing is assigned to one processor among a plurality of proc...

Claims

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Application Information

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IPC IPC(8): G06F13/24
CPCG06F13/26
Inventor 大政崇
Owner PANASONIC CORP
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