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Method for planarization of wafer surface

A surface flattening and wafer technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as the inability to obtain a good surface flattening effect, and achieve improved wafer surface flatness and good surface flatness. effect of effect

Inactive Publication Date: 2011-08-03
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Abstract
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  • Application Information

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Problems solved by technology

[0009] The embodiment of the present invention provides a wafer surface planarization method to solve the problem that the wafer surface planarization process in the prior art cannot obtain a good surface planarization effect

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  • Method for planarization of wafer surface
  • Method for planarization of wafer surface
  • Method for planarization of wafer surface

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Embodiment Construction

[0029] The surface of the wafer has steps due to the ups and downs caused by the metal layer. In order to improve this undulating appearance, it is necessary to planarize the wafer surface. In the wafer surface planarization method provided by the embodiment of the present invention, after the SOG layer is spin-coated, an etching-back method is used to improve the flatness of the wafer surface, so as to obtain a better wafer surface planarization effect. Its process is as follows figure 2 As shown, the execution steps are as follows:

[0030] Step S101: Depositing a first silicon dioxide layer on the surface of the stepped wafer.

[0031] Deposit a layer of SiO on the stepped wafer surface by chemical vapor deposition (CVD) 2 . The thickness of the deposited silicon dioxide layer is 2000A-3000A.

[0032] Step S102: Spin-coating a spin-on-glass SOG layer on the silicon dioxide layer.

[0033] The thickness of the spin-coated SOG depends on the height of the steps. Genera...

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Abstract

The invention discloses a method for planarization of a wafer surface. The method comprises the following steps of: depositing a first silicon dioxide layer on the wafer surface which has a step; spinning a spin on glass (SOG) layer over the silicon dioxide layer, wherein an upper surface of the SOG layer at a non-step position is higher than the step of the wafer surface; baking a wafer on whichthe SOG later is spun at a high temperature; etching the SOG layer and the silicon dioxide layer on the wafer surface by adopting a selected etching rate selection ratio to acquire the planeness of the wafer surface which meets a design requirement, and depositing a second silicon dioxide layer on the etched SOG layer. By the method, the planeness of the coated wafer surface is improved in an etching mode after the SOG layer is spun, so that a better surface planarization effect can be achieved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for planarizing the surface of a wafer by using spin-on-glass (Spin On Glass, SOG) to planarize the surface of the wafer. Background technique [0002] For the traditional wafer preparation method using single aluminum back-end process, boron phosphorus oxide reflow is usually used to improve the problem of poor flattening effect of the wafer surface caused by the existence of steps in the preparation process. Planarized wafer surface quality. [0003] With the increasing demand for multi-aluminum in the back-end process of wafer preparation, there are more and more requirements for flattening steps on the wafer. The above-mentioned process using boron phosphorus oxide reflow can no longer meet the requirements for flattening steps. . [0004] Spin-on-glass SOG is the best material of choice to improve wafer surface planarization. It is a liquid di...

Claims

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Application Information

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IPC IPC(8): H01L21/316H01L21/3105H01L21/311
Inventor 陈建国席华萍
Owner PEKING UNIV FOUNDER GRP CO LTD