Memory readout scheme using separate sense amplifier voltage
A technology of sense amplifier and memory, applied in the field of storage circuit, can solve the problems of unrealistic, timing deviation, slow response and uncomfortable storage operation, etc.
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[0021] The making and using of preferred embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the disclosure.
[0022] figure 1 is a schematic diagram of an exemplary memory circuit with independent sense amplifier voltages. The memory 100 includes a memory cell 102 connected to a data line DL 103 . The memory 100 is set with a first voltage, for example, VDD. The storage unit 102 stores information for a bit (ie, a logical 1 or a logical 0). PMOS transistor 104 is connected to precharge signal RSP (ie, read data line reset) to precharge DL 103 to logic 1 for read operations.
[0023] A read cycle for the memory 100 is initiated by holding RSP to a logic 0 and enabling the ...
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