Single chip structured programmable logic device with resistance random access memory (RAM) module

Abstract

The invention belongs to the technical field of programmable logic device and particularly discloses a programmable logic device. The programmable logic device comprises an address circuit module (310), a comparison unit (320), an SRAM (Static Random Access Memory) module (380), a logic array (390) and a resistance RAM module (370) which is used for overcoming the soft error rate in the SRAM module, wherein the resistance RAM module realizes single chip integration with the address circuit module, the comparison unit, the SRAM module and the logic array. The programmable logic device not only can overcome the SER (Symbol Error Rate) problem in the SRAM, but also has the characteristics of single chip, small size, radiation resistance, low power consumption and low cost.

Description

technical field [0001] The invention belongs to the technical field of programmable logic devices, and in particular relates to a programmable logic device which overcomes the soft error rate (Soft Error Rate, SER) problem in a volatile (Volatile) memory module through a nonvolatile (Nonvolatile) memory module, especially relates to The non-volatile memory is a resistive RAM and a single-chip programmable logic device. Background technique [0002] PLD is the abbreviation of Programmable Logic Device (Programmable Logic Device), and the generalized programmable logic device also includes FPGA (Field Programmable Gate Array, Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device, complex programmable logic device). Programmable logic can complete the function of any digital device, up to a high-performance CPU, down to a simple 74 circuit, can be realized with PLD. A programmable logic device is like a blank sheet of paper or a pile of building blocks. En...

AI Technical Summary

Problems solved by technology

The disadvantage of method (1) is: when most soft errors occur, the judgment circuit will get wrong judgments, resulting in FPGA configuration errors

The disadvantage of the (2) method is: ECC can only correct errors when the number of units with soft errors is small

At the same time, the common technical defects of the two methods are: the programmable logic chip requires a large number of decision circuits and CRC / ECC circuits, which increases the chip area and reduces the circuit operating speed.

According to the storage principle of SRAM and Flash, Flash memory and SRAM are easy to generate SER under radiation conditions; at the same time, Flash memory uses floating gate technology. In the existing semiconductor manufacturing technology, it is difficult to integrate Flash memory and SRAM in the same chip. of

therefore, figure 1 The programmable logic device 100 shown is difficult to implement a single-chip structure

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