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Current mirror evaluation dynamic circuit

A dynamic circuit, current mirror technology, applied in the direction of regulating electrical variables, instruments, control/regulating systems, etc.

Inactive Publication Date: 2013-02-06
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In this current mirror evaluation dynamic circuit structure, there are still some problems:
[0012]2. Since the current of the input network determines the output state, there is no need for the input dynamic node, and the pre-charged Mpre1 tube in the current mirror evaluation structure It can be omitted, and the existence of the pre-charged Mpre1 tube will make the pull-down current of the input network too small and affect the normal operation of the circuit

Method used

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  • Current mirror evaluation dynamic circuit
  • Current mirror evaluation dynamic circuit
  • Current mirror evaluation dynamic circuit

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Experimental program
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Embodiment Construction

[0037] Including: an input network, a primary current mirror circuit, and a secondary current mirror circuit, the input network is connected to a holding tube through the primary current mirror circuit, the grid of the holding tube is directly connected to the secondary current mirror circuit, and the holding tube The drain of the inverter is used as the output of the whole circuit by connecting the inverter.

[0038] The primary current mirror circuit includes: three NMOS transistors: M1, M5 and M2, the output end of the input network is connected to the drain end of the M1, and the drain end of the M5 is used as a dynamic node, connected to the holding The drain end of the tube, the drain end of M2 is connected to the secondary current mirror circuit, and the primary current mirror circuit is also connected to the drain end of the first pre-charging tube.

[0039]The secondary current mirror circuit includes: two PMOS transistors: M3 and M4, the drain of M3 is connected to t...

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Abstract

The invention discloses a current mirror evaluation dynamic circuit comprising an input network, a primary current mirror circuit and a secondary current mirror circuit, wherein the input network is connected with a retaining tube through the primary current mirror circuit; a grid electrode of the retaining tube is directly connected with the secondary current mirror circuit; a drain electrode of the retaining tube is connected with a phase inverter to serve as the output end of the whole circuit; and a power supply end of the input network is directly connected with work voltage VDD (Voltage Drain Drain). According to the current mirror evaluation dynamic circuit, the evaluation speed is improved; a pre-charging tube in the input stage is omitted so as to increase pull-down current in the input stage; and the phenomenon that the work of the circuit is influenced due to over-low current is avoided.

Description

technical field [0001] The invention relates to the technical field of dynamic circuits in CMOS circuits, in particular to a current mirror evaluation dynamic circuit. Background technique [0002] Traditional CMOS static circuits suffer from inherent speed limitations due to the input signal driving both NMOS and PMOS transistors. The input signal of the CMOS dynamic circuit only needs to drive the NMOS (or PMOS) transistor, so it has great advantages over the static circuit in terms of speed and area. [1] . However, for a large-in OR gate, such as figure 1 As shown, the traditional dynamic circuit [2] The dynamic node (DYN) capacitance will increase as the fan-in increases, which slows down the speed at which the input network can pull down the dynamic node, and in severe cases cannot pull it down to a valid low level. At the same time, serious leakage current requires a relatively large keeper (Keeper) [3] , which also increases the competing current during pulldown,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05F3/26
Inventor 贾嵩孟庆龙杨凯王源张钢刚
Owner PEKING UNIV