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Multi-channel direct memory access (DMA) controller with arbitrator

A technology of DMA controller and arbiter, applied in instruments, electrical digital data processing, etc., can solve the problems of slow transmission speed, no arbitration strategy, unable to cope with the simultaneous initiation of DMA transmission by multiple channels, etc., to improve the speed and expand the application. range effect

Inactive Publication Date: 2011-11-02
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The device described in this Chinese patent has the following disadvantages: ① There is only one multiplexing module for multi-channel control, which cannot cope with the situation that multiple channels initiate DMA transmission at the same time, and there is no flexible arbitration strategy to choose from; ② Each DMA The basic transmission basically needs two cycles, and the transmission speed is relatively slow, so it is not suitable for high-speed data transmission occasions

Method used

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  • Multi-channel direct memory access (DMA) controller with arbitrator
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  • Multi-channel direct memory access (DMA) controller with arbitrator

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Embodiment Construction

[0043] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0044] figure 2It is the overall block diagram of the improved DMA system of the present invention. As shown in the figure, there are two sets of buses in the system, the data lines of the two sets of buses are respectively used as the read data bus and the write data bus, and the address lines of the two sets of buses are respectively used as the source address bus and the destination address bus.

[0045] figure 2 It also shows the structure of the whole system, including CPU, DMA controller, on-chip and off-chip memory, high-speed I / O, bus bridge and low-speed peripherals, among which:

[0046] The CPU is connected to the high-speed bus, processes the DMA transfer request sent by the DMA controller, and grants the DMA controller the right to use the bus.

[0047] The DMA controller is connected to the high-speed bus, processes...

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Abstract

The invention discloses a multi-channel direct memory access (DMA) controller with an arbitrator. The conventional controller is lower in transmission speed and is inapplicable to high-speed data transmission occasions. The multi-channel DMA controller comprises a DMA engine, two main equipment interfaces, a slave equipment interface, a channel arbitrator and a register stack, wherein the main equipment interfaces are connected with a bus and the DMA engine; the slave equipment interface is connected with the bus and the DAM engine; the channel arbitrator is connected with the DMA engine and a multi-path switch; an arbitration strategy register, a rotary algorithm register, a state register, a fixed priority level register and a rotary priority level register are involved; and the register stack is connected with the DMA engine and the multi-path switch and divided into a main control state register and all channel registers. The multi-channel DMA controller is high in DMA transmission speed and applicable to the high-speed data transmission occasions and expands the application range.

Description

technical field [0001] The invention relates to a DMA controller, in particular to a multi-channel DMA controller with an arbiter. Background technique [0002] In the data processing system and SOC chip with CPU as the main control device, data transmission usually adopts three ways. ①Polling mode: The CPU periodically detects the state of the slave device, and takes out data from the source device at an appropriate time and writes it into the destination device. When using this method, it will take up a lot of processor time, and the data transmission speed is limited by the execution time of CPU instructions. ② Interrupt mode: When the slave device needs to transmit data, it sends an interrupt request to the CPU, and the CPU executes the data transmission task after responding. When using this method, the CPU does not have to actively query the status of the slave device, which saves part of the processor time, but the transmission process is still controlled by the CPU...

Claims

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Application Information

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IPC IPC(8): G06F13/30
Inventor 沈海斌张俊严军吴翔
Owner ZHEJIANG UNIV
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