Dynamic memory controller and method for increasing bandwidth utilization rate of dynamic memory

Abstract

The invention provides a dynamic memory controller and method for increasing the bandwidth utilization rate of a dynamic memory. The method comprises the following steps: the dynamic memory controller receives and stores an access request of each access port while transmitting an operating instruction transmitted to the dynamic memory and transmits a next stored operating instruction to the dynamic memory after the transmission of the operating instruction which is being transmitted is finished. By adopting the technical scheme provided by the invention, the technical problem of low bandwidth utilization rate of the dynamic memory in the prior art can be effectively solved.

Description

technical field [0001] The invention relates to a dynamic memory DRAM (Dynamic Random Access Memory) controller, in particular to a dynamic memory controller and a method for improving dynamic memory bandwidth utilization. Background technique [0002] The schematic diagram of the DRAM controller is shown in figure 1 As shown, the controller includes two interfaces: the interface to the access port and the interface to the DRAM chip. [0003] When the controller reads and writes the DRAM, it is limited by its conditions. After sending the read and write addresses, it needs a fixed delay before reading or writing data from the DRAM. Taking DDR3-800 as an example, for DDR3-800 devices, under 400M clock, at least 5 clock cycle delays are required to read or write data from DDR3 SDRAM after sending out the read and write address. And because DDR3 SDRAM is in the same Bank (unit) every time, when reading and writing operations on a new line, you need to close the opened line (P...

AI Technical Summary

Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide a dynamic memory controller and method for improving dynamic memory bandwidth utilization, which can effectively solve the technical problem of low dynamic memory bandwidth utilization in the prior art

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