Inter-integrated circuit (I2C) transmission method and device

Abstract

The invention discloses an inter-integrated circuit (I2C) transmission method and an I2C transmission device, which are used for realizing the high-speed transmission of an I2C controller. The device comprises a central processing unit (CPU) interface unit connected with a CPU, and an I2C master unit and an I2C slave unit which are connected with the CPU interface unit, wherein the CPU interface unit is used for configuring the device in a master state or a slave state and the working mode of the device in a high speed (Hs) mode through the CPU; the I2C master unit is used for switching the device to the Hs mode when the CPU interface unit configures the device in the master state and realizing the master operation of the device; and the I2C slave unit is used for switching the device to the Hs mode when the CPU interface unit configures the device in the slave state and realizing the slave operation of the device. By the device, high-speed I2C transmission is realized.

Description

technical field [0001] The invention relates to the field of computer communication, in particular to a method for realizing high-speed I 2 C transfer method and a way to achieve high-speed I 2 C transmission means. Background technique [0002] In practical applications, higher bus speed and lower power supply voltage consumption are required. In order to meet these requirements, on the basis of fast mode or standard mode (ie F / S mode), I 2 C (Iinter-Integrated Circuit, interconnection bus between integrated circuits) version 2.0-1998 adds a high-speed mode (ie Hs mode), which increases the bit rate of data transmission to 3.4Mbit / s. Subsequently, I 2 C version 2.1-2000 has made some improvements to the Hs mode. For example, the clock signal SCL (System Clock Line) can be extended after the repeated start condition of the Hs mode. There are no special requirements for some timing parameters in the Hs mode. strict. The main purpose of constructing the Hs mode is to incr...

AI Technical Summary

Problems solved by technology

I 2 When the C bus works in Hs mode, the biggest factor affecting its work is the transient response of the level on the SCL bus from low to high, because the bus pull-up resistors in standard mode and fast mode cannot produce faster rise times, and the voltage The time delay required for leveling from low to high is relatively large. At present, in order to improve the problem of large transient response time delay from low to high on the SCL bus, the I 2 The C-bus specification makes the following improvements:

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