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Method and device for implementing hybrid automatic repeat request memory dynamic scheduling

A hybrid automatic retransmission and dynamic scheduling technology, which is applied in transmission systems, digital transmission systems, and error prevention/detection using return channels to improve transmission efficiency, simplify implementation, and achieve dynamic scheduling.

Inactive Publication Date: 2011-12-07
SANECHIPS TECH CO LTD
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  • Claims
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Problems solved by technology

[0006] However, this method of designing small-capacity memory on-chip and designing large-capacity memory off-chip needs to be matched with an effective memory scheduling method

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  • Method and device for implementing hybrid automatic repeat request memory dynamic scheduling
  • Method and device for implementing hybrid automatic repeat request memory dynamic scheduling
  • Method and device for implementing hybrid automatic repeat request memory dynamic scheduling

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Embodiment Construction

[0049] The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and preferred embodiments. The following examples are only used to illustrate and explain the present invention, but not to limit the technical solution of the present invention.

[0050] The structure of the embodiment of the receiver implementing the dynamic scheduling of HARQ memory in the present invention is as follows figure 1 As shown, it includes a multi-input multi-output (MIMO, Multi-Input Multi-Output) demodulation module and a decoder connected to each other; wherein, the decoder includes a HARQ module, an operation module (Viterbi), a HARQ memory, and a HARQ buffer (Buffer ), the HARQ memory includes on-chip memory (On chip memory) and off-chip memory (Off chip memory), and the on-chip memory of the decoder is connected to the off-chip memory through a bus (bus).

[0051] Since the LLR output of the MIMO demodulation module has a...

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Abstract

A method and device for implementing dynamical scheduling of a hybrid automatic repeat request (HARQ) memory are disclosed in the present invention, wherein, the method relates to a decoder which includes an on-chip memory, an off-chip memory and a buffer. The method includes: after combining input data and data in the buffer in the input period, the decoder buffers the combined data in the on-chip memory for decoding and output; when the on-chip memory is full, the combined data is written and buffered in the off-chip memory through the buffer. The invention greatly promotes transmission efficiency of the bus, and effectively enables the dynamical scheduling of HARQ data between the on-chip memory and the off-chip memory. Furthermore, a dynamical scheduling method for priorly scheduling the first depleted buffer is provided, which greatly simplifies the implementation of the system, and satisfies the requirement of the system for combining the HARQ data.

Description

technical field [0001] The invention relates to a Hybrid Automatic Repeat reQuest (HARQ, Hybrid Automatic Repeat reQuest) technology in the field of wireless communication, in particular to a method and a device for realizing dynamic scheduling of HARQ memory in a broadband wireless communication system. Background technique [0002] HARQ technology is the key technology of 3G, 4G and even future broadband wireless communication. Has been widely used. [0003] A typical wireless communication channel changes randomly, and has the characteristics of frequency selectivity and time variation. In the design of the wireless communication system, it is necessary to take the random variation factor of the wireless channel into consideration. And a more optimal design can use this randomness to improve the performance and capacity of the system. One of the important ideas is to change the signal transmission rate by dynamically adjusting the modulation mode and coding rate accord...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/18H04W72/12
CPCH04L1/00H04L1/1812H04W72/12H04L1/1845H04L1/18
Inventor 任天民
Owner SANECHIPS TECH CO LTD
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