Method and device for improving read operation efficiency of synchronous dynamic random access memory controller

Abstract

A synchronous dynamic random access memory controller is disclosed, and which is configured to: after receiving a writing operation request from a user, choose one or more mirror spaces used for backing up writing operation data, and said mirror spaces are the address spaces that locate in the synchronous dynamic random access memory in the different memory arrays from the writing address of the writing operation request, and process a plurality of reading operation requests in parallel, and the mirror spaces selected for various reading operation requests for reading data are located in different arrays in the synchronous dynamic random access memory. Said synchronous dynamic random access memory controller includes an operation generator module and a mirror operation process module connected with each other. A method and an apparatus for reading data with the synchronous dynamic random access memory controller are also disclosed. The present invention can increase the speed of processing the reading operation requests from a user with the synchronous dynamic random access memory controller, and reduce the delayed processing time of the reading operation request.

Description

technical field [0001] The invention relates to the technical field of data read operations, in particular to a method and a device for improving the read operation efficiency of a synchronous dynamic random access memory controller. Background technique [0002] With the development of multimedia services in communication networks, the network's demand for communication transmission bandwidth is also increasing rapidly. With the rapid increase of network data volume, the processing technology for massive data has become the bottleneck of network development. In the processing of a large number of data packets, the access to the external memory becomes the bottleneck of the processing speed of the data packets. Effectively improving the efficiency of external memory access becomes the key to the design of external memory access controllers. The method used in the prior art is to use a Synchronous Random Access Memory (SRAM) type of device. This type of device can meet the d...

AI Technical Summary

Problems solved by technology

The method used in the prior art is to use a Synchronous Random Access Memory (SRAM) type of device. This type of device can meet the demand for memory access bandwidth, but the characteristics of small capacity and high cost have affected its availability. widely used

However, the large-capacity and low-cost synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, referred to as SDRAM) is due to the limitation of the device itself, so that the access efficiency of the traditional controller is very low in certain access methods.

The solutions in the prior art generally improve the access efficiency by effectively scheduling the accessed address space, but this scheduling method often causes the order in which the user issues access to be different from the order in which the controller executes, resulting in out-of-order situations, resulting in access requests be delayed

These defects will also cause the complexity of scheduling algorithm design and the instability of efficiency, affecting the overall stability of the system

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