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Sampling hold circuit and method

A technology of sampling and holding circuit and sampling capacitor, which is applied in the direction of electrical components, electrical signal transmission systems, signal transmission systems, etc., can solve the problems affecting the accuracy of sampling and holding circuits, and achieve the effect of eliminating the cumulative effect

Inactive Publication Date: 2013-11-27
成都铭恒星通科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the operational amplifier is always in the working state of signal hold, the offset error will always accumulate on the input signal, affecting the accuracy of the sample and hold circuit

Method used

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  • Sampling hold circuit and method
  • Sampling hold circuit and method
  • Sampling hold circuit and method

Examples

Experimental program
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Embodiment Construction

[0016] see figure 2 , The sample-and-hold circuit of the present invention comprises an operational amplifier AMP, a first-stage sample-and-hold circuit, a second-stage sample-and-hold circuit, a first input terminal Vinp, a second input terminal Vinn, a first output terminal Vo2n and a The second output terminal Vo2p. The operational amplifier AMP has a positive input terminal Vip, a negative input terminal Vin, a positive output terminal Vop and a negative output terminal Von. The first-stage sample-and-hold circuit includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, An eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, a twelfth switch K12, a common mode voltage terminal Vcom, a first capacitor C11, a second capacitor C12, A third capacitor C13 and a fourth capacitor C14. The second-stage sample-and-hold circuit includes a thirteenth switch K13, a ...

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Abstract

The invention discloses a sampling hold circuit, which comprises an operational amplifier, and a first-stage sampling hold circuit and a second-stage sampling hold circuit which are connected with the operational amplifier respectively, wherein the operational amplifier is provided with a positive input end, a negative input end, a positive output end and a negative output end; the sampling hold circuit has a first phase and a second phase; the second-stage sampling hold circuit comprises a sampling capacitor; when the sampling hold circuit is at the first phase, the sampling capacitor is connected between the positive input end and the negative output end of the operational amplifier; and when the sampling hold circuit is at the second phase, the sampling capacitor is connected between the negative input end and the positive output end of the operational amplifier. The invention also provides a sampling hold method. The circuit has a simple structure; and the accuracy of the sampling hold circuit is improved.

Description

technical field [0001] The invention relates to a sample-and-hold circuit and method, in particular to a sample-and-hold circuit and method capable of eliminating the accumulative effect of offset errors of operational amplifiers. Background technique [0002] The sample-and-hold circuit is a circuit used in the analog / digital conversion system. Its function is to collect the instantaneous value of the analog input voltage at a certain moment, and to keep the output voltage constant during the conversion of the analog-to-digital converter for the analog-to-digital convert. [0003] see figure 1 , figure 1 Shown is an existing two-stage sample-and-hold circuit, which is formed by cascading two separate sample-and-hold circuits. The working principle of each stage of sample-and-hold circuit is as follows: In the PH1 phase, capacitor C11 and capacitor C12 sample the input signal; In the PH2 phase, the capacitor C13 and the capacitor C14 hold the input signal; since the opera...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/54
Inventor 朱国军
Owner 成都铭恒星通科技有限公司