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Shallow trench isolation structure and method for forming same, semiconductor structure and method for forming same

An isolation structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as easy leakage current, and achieve the effect of easy integration and simple process

Active Publication Date: 2016-06-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The problem solved by the present invention is to provide a shallow trench isolation structure and its forming method; to provide a semiconductor structure and its forming method to solve the problem that the existing NMOS transistors are prone to leakage current in the radiation environment or after radiation

Method used

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  • Shallow trench isolation structure and method for forming same, semiconductor structure and method for forming same
  • Shallow trench isolation structure and method for forming same, semiconductor structure and method for forming same
  • Shallow trench isolation structure and method for forming same, semiconductor structure and method for forming same

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Embodiment Construction

[0054] It can be seen from the background art that the performance of the existing NMOS transistors in the radiation environment is not good enough, and leakage current is easily generated in the radiation environment. The inventor studies the problems referred to above and thinks that the reason that the performance of existing NMOS transistors is not good enough is that radiation (charged particles such as α particles, β particles, and protons can directly cause material ionization; particles such as X-rays, γ photons, and neutrons do not Charged, but when it interacts with matter, "secondary particles" are generated to ionize the matter. All these phenomena are collectively referred to as ionizing radiation, or radiation for short. Radiation will cause atoms in the active region of the MOS transistor, as well as in the shallow trench isolation structure The atoms are ionized to generate a large number of electron-hole pairs. The electrons in the electron-hole pairs generated...

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Abstract

A shallow trench isolation structure, comprising: a semiconductor substrate having a groove in the semiconductor substrate; an insulating dielectric layer covering the surface of the groove; a conductive layer located on the surface of the insulating dielectric layer, the conductive layer Fill the grooves. The present invention also provides a method for forming the above shallow trench isolation structure. A semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate has a groove, and device regions located on both sides of the groove; an insulating dielectric layer covering the surface of the groove; a conductive layer, the conductive layer fills the groove, and the conductive layer is electrically connected to a low potential. The present invention also provides a method of forming the above-mentioned semiconductor structure. The invention can improve the performance of the semiconductor device and avoid leakage current.

Description

technical field [0001] The invention relates to the semiconductor field, in particular to a shallow trench isolation structure and a forming method thereof, a semiconductor structure and a forming method thereof. Background technique [0002] A shallow trench isolation structure (Shallow Trench Isolation, STI) is a commonly used isolation structure. The principle of forming the shallow trench isolation structure is to etch the silicon substrate into a trench corresponding to the shallow trench isolation structure, and fill the trench with a dielectric material. [0003] The active region isolation structure of the MOS transistor also mostly adopts the shallow trench isolation structure, and more relevant information about the shallow trench isolation structure can be found in the US patent No. US7112513. [0004] Existing methods for forming NMOS transistors include: [0005] refer to figure 1 , providing a semiconductor substrate 100, the semiconductor substrate 100 bein...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
Inventor 李乐
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP