Three-dimensional (3D) integrated circuit structure and method for detecting alignment of chip structures

Abstract

The invention discloses a three-dimensional (3D) integrated circuit structure and a method for detecting the alignment of chip structures. The circuit structure comprises a first chip structure, wherein the chip structure comprises a first semiconductor substrate, a first insulation layer and a first detection structure; the first detection structure comprises detection base bodies distributed on two sides of the first insulation layer; each detection base body comprises a first conductor, at least two second conductors and at least one third conductor; the first conductors are positioned on one side of the first insulation layer and connected with one-ends of the second conductors; the third conductors are formed between the corresponding second conductors and insulated from the second conductors; the ends, away from the first conductors, of the third conductors are changed gradiently; the opposite lengths of the third conductors and the second conductors are equal to each other; and in a direction of the third conductors, distances between projections of the ends, away from the first conductors, of the third conductors corresponding to the detection base bodies on two sides are equal to each other. The invention can be used for optimizing the alignment among the chip structures during manufacturing of the integrated circuit.

Description

technical field [0001] The invention relates to the field of semiconductors, and more specifically, to a 3D integrated circuit structure and a method for detecting whether the chip structure is aligned. Background technique [0002] As the size of semiconductor devices becomes smaller and smaller, the development trend of integrated circuits is to integrate more and more electronic devices on smaller and smaller chips. 3D integrated circuits require bonding between chips, chips and wafers, and wafers. However, due to alignment errors during the bonding process of chips or wafers, problems such as short circuit or interconnection open circuit may be caused, the reliability of integrated circuits is greatly reduced, and the cost of integrated circuit manufacturing is also greatly increased. [0003] In view of this, it is necessary to provide a novel 3D integrated circuit structure and a method for detecting whether the chip structure is aligned, so as to increase the reliabi...

AI Technical Summary

Problems solved by technology

However, during the bonding process of chips or wafers, due to alignment errors, problems such as short circuits or interconnect openings may occur, greatly reducing the reliability of integrated circuits, and greatly increasing the cost of integrated circuit manufacturing.

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