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Method for preventing punch through voltage reduction of memory and memory thereof

A technology of punch-through voltage and memory, which is applied to circuits, electrical components, electric solid-state devices, etc., can solve the problems of lowering the punch-through voltage of the memory and affecting the performance of the device, and achieve the effect of preventing the punch-through voltage and the

Active Publication Date: 2014-07-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In practice, it is found that the punch-through voltage of the memory with the above structure is reduced, which affects the device performance

Method used

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  • Method for preventing punch through voltage reduction of memory and memory thereof
  • Method for preventing punch through voltage reduction of memory and memory thereof
  • Method for preventing punch through voltage reduction of memory and memory thereof

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Embodiment Construction

[0031] The inventors have found that the decrease in the punch-through voltage of the prior art memory is due to leakage current in the semiconductor substrate region between adjacent word lines and adjacent bit lines of the memory. Specifically, since the dopant ions in the diffused bit line region (ie bit line) pass through the semiconductor substrate between the adjacent word line and the adjacent bit line, in the semiconductor substrate between the adjacent word line and the adjacent bit line A leakage current is formed, resulting in a decrease in punch-through voltage between adjacent word lines and a decrease in punch-through voltage between adjacent bit lines.

[0032] The inventor considers performing inverse ion implantation on the semiconductor substrate between adjacent word lines and adjacent bit lines, implanting dopant ions into the semiconductor substrate to form a potential barrier region to prevent the diffusion of the bit line region The dopant ions pass thro...

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Abstract

The invention provides a method for preventing punch through voltage reduction of a memory. The method is characterized by: providing a semiconductor substrate on which a plurality of word lines and a plurality of bit lines are formed; forming a mask layer which exposes the semiconductor substrate between the adjacent word lines and the adjacent bit lines on the word lines and the bit lines; taking the mask layer as a mask and performing insulation ion implantation to the semiconductor substrate exposed by the mask layer; annealing the ion implanted in the semiconductor substrate so as to form an anti-punch through zone in the semiconductor substrate. By using the method of the invention, punch through voltage reduction of the memory can be prevented.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preventing memory punch-through voltage from decreasing and a memory. Background technique [0002] Memory is a semiconductor device used to store data or data. In the storage of data materials, the capacity of the memory is represented by bits (Bit). Each unit used to store data is called a storage unit (Cell). The storage units are arranged in an array in the memory, and each combination of row and column represents a specific storage unit address. Wherein, multiple memory cells in the same row or column are connected in series through a common wire. Wherein, the wires connecting memory cells in the same row (or the same column) in series are called word lines, and the wires related to data transmission are called bit lines. [0003] A memory is disclosed in Chinese patent application No. 20061014728.4, please refer to figure 1 . Existing memories incl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76H01L21/266H01L23/532
Inventor 吴兵常建光王永刚衣冠君马赛罗
Owner SEMICON MFG INT (SHANGHAI) CORP