Dual-edge-triggered state-retention scan flip-flop (DET-SRSFF)

A technology of double edge triggering and scanning triggering, which is applied in pulse technology, pulse generation, electrical components, etc., can solve the problems of increased power consumption, unsatisfactory high level, and PMOS tube cannot be completely turned off, and achieves a simplified structure. , the effect of low power consumption advantage

Inactive Publication Date: 2012-02-08
PEKING UNIV
View PDF2 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] 5. Due to the low-level technology, the high level of the latch may not be ideal, which will cause the PMOS tube connected to the output to not be completely turned off, increasing power consumption
[0019] But there is still a problem with the above structure: when going to sleep, CG will change from 0 to 1. It was expected that P will stop generating pulses immediately

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Dual-edge-triggered state-retention scan flip-flop (DET-SRSFF)
  • Dual-edge-triggered state-retention scan flip-flop (DET-SRSFF)
  • Dual-edge-triggered state-retention scan flip-flop (DET-SRSFF)

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0043] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0044] The present invention is to the pulse generating circuit of the DET-SRSFF of Fig. 1 (a) and the static latch and the input and output circuit of the DET-SRSFF of Fig. 1 (b) (specifically, the LFB circuit as the output structure is wherein figure 2 ) were improved respectively.

[0045] The improvement to Figure 1(b) is as follows: From Figure 1(b), we can see that the static latch part only disconnects the power supply VCCH due to the gate control tube, so the latched level will only appear high level loss without low level loss. Therefore, the LFB does not need to consider the situation that the NMOS cannot be completely turned off. MN1 and MN2 can be deleted, a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to the technical field of integrated circuits and discloses a dual-edge-triggered state-retention scan flip-flop (DET-SRSFF), which is characterized by comprising a pulse generating circuit and a static-state latch circuit which are connected with each other, wherein the static-state latch circuit comprises a leakage feedback pulse structure. According to the invention, leakage feedback buffer (LFB) circuits in the pulse generating circuit of the traditional DET-SRSFF as well as a static-state latch and input-output circuit are improved, the structure of the LFB is simplified on the premise of completely maintaining the low-power-consumption advantage of the DET-SRSFF. In addition, the pulse generating circuit is modified, and generated redundant pulses are removed. Finally, a simulation result from high-precision simulation program with integrated circuit emphasis (HSPICE) shows that the improved structure has advantages in the aspects of both power consumption and speed. A power consumption lagged product is reduced by 19.56%, and the improved DET-SRSFF is more suitable to meeting requirements of the development of the integrated circuit on a trigger.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a dual-edge-triggered state-holding scannable flip-flop. Background technique [0002] With the decrease of the characteristic size of the integrated circuit process and the increase of the operating frequency of the circuit, reducing the leakage power consumption of the circuit has become the focus and difficulty of the integrated circuit design. The clock system consisting of sequential units (flip-flops and latches) and clock networks is one of the largest sources of power consumption in VLSI (Very Large Scale Integration) systems. Statistics show that about 30% to 60% of the leakage power is generated by the clock system, so reducing the power consumption of flip-flops has far-reaching significance (see literature [2]). In the literature [1], the dual-edge triggered state-retention scan flip-flop (DET-SRSFF) designed by H.Karimiyan, S.M.Sayedi and H.Saidi is aime...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03K3/011H03K3/037
Inventor 贾嵩李夏禹刘俐敏
Owner PEKING UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap