Phase discriminator realizing circuit and phase discriminator clock generating method

Abstract

Disclosed in the embodiments of present invention are a phase discriminator implementation circuit and a phase discriminator clock generation method, which relate to the technique field of telecommunication, with which the phase discriminator clock fitted for the session clock is generated by relatively simple processing. The method comprises: the rate comparator compares the rate of writing session data to cache with the rate of reading session data from cache by phase discriminator, to determine the frequency offset absolute value and rate of the session clock correspondent to the session data, and sends instructions to the pattern generator according to comparison results; the pattern generator generates a fast clock gap pattern or slow clock gap pattern according to the instructions; the frequency changer performs frequency changing on the clock of the phase discriminator according to the fast clock gap pattern or the slow clock gap pattern, and reads next session data from cache with the clock of phase discriminator which frequency is changed. The present invention is mainly used for the generation of the phase discriminator clock.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a phase detector realization circuit and a phase detector clock generation method. Background technique [0002] With the continuous improvement of the OTN network, the OTN network can support more and more types of services. Therefore, in the OTN network, there are services that need to be transmitted to the high-speed OTUk network, or VC container, or an asynchronous backplane OTUk_L. In order to make the clock of this service match the clocks of these containers, it can be implemented by using the ODUk (Optical Path Data Unit) of the VC container clock. [0003] In the above solution, when the service is transmitted to the ODUk, the ODUK needs to generate an ODUk clock that matches the service clock. Currently, a digital phase-locked loop or an analog phase-locked loop is used to generate an ODUk clock synchronized with a service clock. [0004] Phase-locked loop is t...

AI Technical Summary

Problems solved by technology

[0006] Regardless of whether a digital phase-locked loop or an analog phase-locked loop is used to generate the ODUk clock synchronized with the service clock, an external phase-locked loop needs to be set up, which makes the entire processing process more complicated

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