Single event upset resistant settable scanning structure D trigger

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability.

Active Publication Date: 2012-02-22
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The technical problem to be solved by the present invention is to propose a scanning structure D flip-flop capable of setting anti-single event flip-flops in view of the problem that the anti-single e

Method used

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  • Single event upset resistant settable scanning structure D trigger
  • Single event upset resistant settable scanning structure D trigger
  • Single event upset resistant settable scanning structure D trigger

Examples

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Embodiment Construction

[0031] figure 1 It is a schematic diagram of the logic structure of the anti-single-event flip-flop D flip-flop of the scanning structure that can be set in the present invention. The present invention consists of a clock circuit (such as figure 2 shown), scan control buffer circuit (such as image 3 shown), the master latch (as Figure 4 shown), slave latches (such as Figure 5 shown), the output buffer circuit (such as Figure 6 shown) composition. The present invention has five inputs and two outputs. The five input terminals are respectively CK is the clock signal input terminal, D is the data signal input terminal, SE is the scanning control signal input terminal, SI is the scanning data input terminal and SN is the set signal input terminal; the two output terminals are Q and QN, Q and QN output a pair of opposite data signals. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The main latch receives D, C, CN, SE, SEN, SI, and ...

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Abstract

The invention discloses a single event upset resistant settable scanning structure D trigger, and aims to improve the single event upset resistance of the single event upset resistant settable scanning structure D trigger. The trigger consists of a clock circuit, a scanning control buffer circuit, a master latch, a slave latch and an output buffer circuit; the master latch consists of eighteen P-channel metal oxide semiconductor (PMOS) tubes and eighteen N-channel metal oxide semiconductor (NMOS) tubes; the slave latch consists of twelve PMOS tubes and twelve NMOS tubes; both the master latchand the slave latch are subjected to dual-mode redundancy reinforcement; and C2MOS circuits in the master latch and the slave latch are improved, namely separated into pull-up circuits and pull-down circuits in mutually redundant C2MOS circuits. The single event upset resistant synchronously-settable scanning structure D trigger has strong single event upset resistance, is suitable for a standardcell library of a single event upset resistant reinforcing integrated circuit, and is applied in the fields of aviation, spaceflight and the like.

Description

technical field [0001] The invention relates to a master-slave D flip-flop with a setting structure and a scanning structure, in particular to a D flip-flop with a scanning structure which can be set against a single event upset (signal event upset). Background technique [0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even ...

Claims

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Application Information

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IPC IPC(8): H03K3/013H03K3/02
Inventor 池雅庆梁斌刘必慰李鹏刘祥远孙永节胡春媚陈建军何益百杜延康秦军瑞
Owner NAT UNIV OF DEFENSE TECH
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