D trigger resisting single event upset

An anti-single event and trigger technology, which is applied in the direction of electric pulse generator circuit, pulse generation, electrical components, etc., can solve the problem of low anti-single event flipping ability, and achieve the effect of improving the anti-single event flipping ability

Active Publication Date: 2013-12-11
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is to propose an anti-single-event flip-flop D flip-flop, which can operate at a single event with a higher LET value. Works fine under particle bombardment without generating single event flips

Method used

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  • D trigger resisting single event upset
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  • D trigger resisting single event upset

Examples

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Embodiment Construction

[0026] figure 1 It is a schematic diagram of the logical structure of the anti-single event flip-flop D flip-flop of the present invention. The present invention consists of a clock circuit (such as figure 2 shown), the master latch (as image 3 shown), slave latches (as Figure 4 shown), the first inverter circuit (such as Figure 5 shown) and a second inverter circuit (as Figure 6 shown) composition. The present invention has two input terminals and two output terminals. The two input terminals are CK, which is the clock signal input terminal, and D, which is the data signal input terminal; the two output terminals are Q and QN respectively, and Q and QN output a pair of opposite data signals. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The main latch receives D, C and CN, and the main latch outputs MO after latching D under the control of C and CN. The slave latch receives MO, C and CN, and the slave latch outputs SO and SO...

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Abstract

The invention discloses a D trigger resisting single event upset, and aims to improve the single event upset resistance of the D trigger. The D trigger comprises a clock circuit, a main latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit. the main latch comprises 10 PMOS (P-channel Metal Oxide Semiconductor) tubes and 10 NMOS (N-Mental-Oxide-Semiconductor) tubes; the slave latch comprises 10 PMOS tubes and 10 NMOS tubes; both the main latch and the slave latch adopt bimodule redundant reinforcement; and in the main latch and the slave latch, C2MOS circuits are also improved, that is, pull-up PMOS tubes and pull-down NMOS tubes in redundant relation in each C2MOS circuit are separated. The D trigger has strong single event upset resistance, is suitable for standard cell library for a reinforced integrated circuit resisting single event upset, and is used in the fields of aviation, aerospace, and the like.

Description

technical field [0001] The invention relates to a master-slave D flip-flop, in particular to a D flip-flop resistant to single event upset (signal event upset). Background technique [0002] In the universe, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, it is particularly important to develop advanced anti-singl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/013H03K19/003H03K3/02
Inventor 陈书明梁斌李鹏池雅庆刘必慰何益百陈建军刘真杜延康秦军瑞
Owner NAT UNIV OF DEFENSE TECH
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