Single event upset-resisting scanning structure D trigger capable of setting and resetting
An anti-single event and trigger technology, which is applied in the direction of electric pulse generator circuit, pulse generation, electrical components, etc., can solve the problem of low anti-single event reversal ability
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[0034] figure 1 It is a schematic diagram of the logical structure of a scanning structure D flip-flop that can be set and reset against single event reversal in the present invention. The present invention consists of a clock circuit (such as figure 2 shown), scan control buffer circuit (such as image 3 shown), reset snubber circuit (as Figure 4 shown), the master latch (as Figure 5 shown), slave latches (as Figure 6 shown) and the output buffer circuit (as Figure 7 shown) composition. The present invention has six inputs and one output. The two input terminals are CK is the clock signal input terminal, D is the data signal input terminal, SE is the scan control signal input terminal, SI is the scan data input terminal, SN is the set signal input terminal and RN reset signal input terminal; one The output terminal is Q, that is, the data output signal terminal. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The scan control...
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