Method and system for generating systems-on-a-chip (SoC) verification platform

A verification platform and template generation technology, applied in special data processing applications, instruments, electrical and digital data processing, etc., can solve problems such as poor reusability of verification platforms, save development cycles, and ensure correct results.

Active Publication Date: 2012-04-04
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method and system for genera

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  • Method and system for generating systems-on-a-chip (SoC) verification platform
  • Method and system for generating systems-on-a-chip (SoC) verification platform
  • Method and system for generating systems-on-a-chip (SoC) verification platform

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Embodiment 1

[0036] There are many verification methods for SoC chip verification, such as RVM (Reference Verification Methodology) verification method, VMM (Verification Methodology Manual) verification method, etc. The verification platforms corresponding to different verification methods are also different. Among them, VMM is a verification methodology based on SystemVerilog, which utilizes the advantages of SystemVerilog's object-oriented programming to the greatest extent, and improves the verification productivity through a series of mechanisms. This embodiment will be described by taking the VMM verification platform as an example.

[0037] refer to figure 1 , is a schematic diagram of components of the VMM verification platform in Embodiment 1 of the present invention.

[0038] The VMM verification platform adopts a layered test platform structure, which is divided into signal layer, command layer, function layer, stimulus generation layer and test layer from bottom to top. The v...

Embodiment 2

[0061] The present invention is applicable to SoC bus verification and other function verification of SoC chips. This embodiment will take the establishment of a SoC bus verification platform as an example for illustration.

[0062] According to different bus protocols, the SoC bus structure includes AMBA, AHB, AXI, APB and the mixed bus structure of these protocols. Different SoC chips have different system buses, and the templates involved are not exactly the same. For example, different chips may have an AHB bus architecture, an AXI bus architecture, or a mixed architecture of AHB and AXI; in addition, the number of masters is not exactly the same, and there may be four masters , there may also be 8 main devices; in addition, the algorithm modules are different, they may be different functional modules, or they may have the same function but use IP from different manufacturers or IP developed by themselves, and so on. These uncertainties cause different SoC chips to use di...

Embodiment 3

[0070] refer to Figure 4 , is a structural diagram of a system for generating a SoC verification platform described in Embodiment 3 of the present invention.

[0071] The system mainly includes:

[0072] Script generating unit 41, for writing the same part of different SoC verification platforms into automated scripts;

[0073] The template library 42 is used to preset different parts of different SoC verification platforms into different templates, including generating each template required by the verification platform;

[0074] The configuration unit 43 is used to generate a corresponding configuration file for the SoC chip, and the configuration file includes the configuration information required to generate the SoC chip verification platform;

[0075] The template calling unit 44 is used for automated scripts to extract from the template library 41 according to the content of the configuration file the required templates generated by the SoC chip verification platform...

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Abstract

The invention provides a method and a system for generating a systems-on-a-chip (SoC) verification platform, and aims to solve the problem that the conventional verification platform is low in reusability. The method comprises the following steps of: compiling the same part of different SoC verification platforms to form an automatic script, presetting different parts to form different templates, and putting into a template library; generating a corresponding configuration file for a SoC chip, wherein the configuration file comprises configuration information required by generating the SoC chip verification platform; extracting a template required by generating the SoC chip verification platform from the template library according to the content of the configuration file by using the automatic script; and generating the verification platform corresponding to the SoC chip according to the extracted template by using the automatic script. By the method and the system, different verification platforms can be automatically generated only by configuration without reconstruction, so that the development period of the verification platform is greatly shortened, an engineer can concentrate more time on development of test samples, and the correctness of the chip is ensured.

Description

technical field [0001] The invention relates to chip verification, in particular to a method and system for generating a SoC (Systems-on-a-Chip, system-on-a-chip) verification platform. Background technique [0002] With the advent of the deep submicron era of integrated circuits, the scale of integrated circuits continues to expand, which promotes the development and application of system-on-chip SoCs. Usually, the scale of an SoC chip is around several million gates to tens of millions gates. Facing such a high complexity, verification becomes one of the most difficult and challenging issues in SoC design. [0003] In the verification of SoC, the correctness of the bus must be ensured before the whole chip starts system-level simulation and verification, so the verification of the SoC bus is very important to the verification of the whole chip. With the increase of the scale of SoC chip, the scale of bus inside the chip becomes more and more complex, which brings more and...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06F11/00
Inventor 高勇
Owner WUXI ZGMICRO ELECTRONICS CO LTD
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