Isolation structure and manufacturing method thereof as well as semiconductor device with isolation structure

Abstract

The invention discloses an isolation structure of a semiconductor device, a manufacturing method of the isolation structure and the semiconductor device with the isolation structure, relating to the field of semiconductor manufacture. The isolation structure comprises a groove, a lanthanum-rich oxide layer and an isolation material, wherein the groove is embedded into the semiconductor substrate; the lanthanum-rich oxide layer covers the bottom wall and the side wall of the groove; and the isolation material is positioned in the groove on the lanthanum-rich oxide layer. According to the invention, the lanthanum-rich oxide layer is formed in the isolation structure; a lanthanum element is diffused to a gate dielectric layer, so that the influence caused by the narrow channel effect can be reduced and the threshold voltage of the device can be adjusted. The embodiment of the invention is suitable for a high-k / metal gate process in the semiconductor device process.

Description

technical field [0001] The present invention relates to an isolation structure of a semiconductor device and a manufacturing method thereof, in particular to an isolation structure and a manufacturing method thereof which use a lanthanum-rich oxide layer to reduce the influence caused by the narrow channel effect and simultaneously adjust the threshold voltage . Background technique [0002] As semiconductor technology advances, the size of transistors continues to shrink, increasing the speed of devices and systems. In this size-reduced transistor, the gate dielectric layer such as SiO 2 The thickness also becomes thinner. However, when SiO 2 When the thickness is thin to a certain extent, it will no longer be able to play the role of insulation well, and it is easy to generate leakage current from the gate to the active region. This greatly deteriorates device performance. [0003] For this purpose, instead of conventional SiO 2 / polysilicon gate stack, and proposed ...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to solve at least one of the above-mentioned problems in the prior art, especially to solve the problem that the effectiveness of the gate dielectric layer is affected by the narrow channel effect, which leads to the problem that the threshold voltage of the transistor cannot be effectively reduced

Images