Method for implementing low power hybrid Cache of embedded device

A technology of embedded devices and implementation methods, applied in energy-saving ICT, sustainable buildings, memory address/allocation/relocation, etc., can solve problems such as unable to meet the capacity of embedded devices, achieve high cost performance, avoid performance loss, reduce The effect of power consumption

Inactive Publication Date: 2012-05-16
JIANGSU UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] To sum up, none of the existing Cache design schemes can meet the requirements of small capacity and low power consumption of embedded devices.

Method used

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  • Method for implementing low power hybrid Cache of embedded device
  • Method for implementing low power hybrid Cache of embedded device
  • Method for implementing low power hybrid Cache of embedded device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0054] In this example, if figure 1 As shown, when an embedded device system used to establish electronic medical records runs a new program, it determines whether to enter the following low-power hybrid Cache by calculating the relative signature distance between the original program and the new program, and adding the comparison. for:

[0055] The first step is to set the instruction Cache and data Chche respectively figure 2 The states shown are: initial state S0, reserve large capacity state S1, capacity competition state S2, reserve small capacity state S3, and capacity adjustment state S4. Each state is defined as before.

[0056] The second step is to establish the following counters

[0057] A. The instruction access counter I-AC and the data access counter D-AC are respectively used to count the instruction Cache and data Cache access times in each state within the predetermined time slice;

[0058] B. The effective way counter I-MC of the instruction Cache and t...

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PUM

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Abstract

The invention relates to a method for implementing a low power hybrid Cache of an embedded device, belonging to the field of the hierarchical structure design of the computer memory. The method is performed in the embedded device and comprises the following steps of: configuring the initial states S0 of an instruction Cache and a data Cache, a standby high capacity state S1, a capacity competition state S2, a standby low capacity state S3 and a capacity adjustment state S4, respectively; establishing boundaries and a counter; whenever a program segment changes and a next program segment is started, determining the switching states and related settings of the instruction Cache and the data Cache by determining the following conditions one by one. With the method provided in the invention, once the program segment-based PBCRA reconfiguration algorithm of the method is adopted, the power consumption is reduced by 20.4%-41.7% with seldom increasing hardware; and the Cache jittering is reduced. Besides, as the number of paths of the instruction Cache and the number of paths of the data Cache are variable, the collision deletion can be reduced and the jittering can be avoided; therefore, the stable system operations are ensured.

Description

technical field [0001] The invention relates to a processing method of a buffer memory of an embedded device, in particular to a method for realizing a low-power hybrid Cache of an embedded device, and belongs to the field of computer memory hierarchical structure design. Background technique [0002] Currently, reducing the overall power consumption of battery-powered portable embedded devices has increasing practical significance. In these embedded devices, the power consumption of Cache accounts for about 40% of the overall power consumption, so how to reduce the power consumption of Cache has become a common concern of embedded device designers. [0003] Embedded systems usually use fixed-capacity instruction caches and data caches, but the demands of different programs on instruction caches and data caches are unbalanced, resulting in insufficient capacity of one type of cache and idleness of another type of cache. However, hybrid Cache does not have this problem, but ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F1/20G06F12/0802
CPCY02B60/1225Y02B60/1275Y02D10/00
Inventor 宋余庆陈健美杨旭东
Owner JIANGSU UNIV
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