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Method of manufacturing semiconductor devices

A technology for semiconductors and devices, applied in the field of manufacturing semiconductor devices, can solve the problems of deterioration of reliability and defects of semiconductor devices

Inactive Publication Date: 2012-05-23
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] refer to figure 2 , the grid-line bending phenomenon may cause defects in 40
For example, if a gate line abuts on an adjacent but separated gate line, the power supplied to the gate line may also be supplied to the adjacent gate line, and thus the reliability of the semiconductor device may deteriorate

Method used

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  • Method of manufacturing semiconductor devices
  • Method of manufacturing semiconductor devices
  • Method of manufacturing semiconductor devices

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Experimental program
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Embodiment Construction

[0037] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The accompanying drawings are provided to enable those of ordinary skill in the art to understand the scope of embodiments of the present invention.

[0038] Figure 3A to Figure 3F is a plan view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

[0039] refer to Figure 3A , forming a cell region and a peripheral region on the well-formed semiconductor substrate. Here, the cell area includes a plurality of memory cell block areas storing data, and the peripheral area is an area for programming, reading, and otherwise controlling the memory cells. In addition, an active region AC and an isolation region ISO are defined in the cell region and the peripheral region, and an isolation layer is formed in the isolation region.

[0040] In addition, gate lines are formed in the cell regi...

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PUM

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Abstract

A method of manufacturing semiconductor devices includes forming a plurality of lines arranged in a direction over a semiconductor substrate, forming mask patterns over the semiconductor substrate wherein the mask patterns intersect the lines, and forming junctions in the semiconductor substrate between the lines by performing an ion implantation process.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2010-0114395 filed on November 17, 2010, the entire contents of which are incorporated herein by reference. technical field [0003] Exemplary embodiments of the present invention generally relate to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of reducing / minimizing the occurrence of a gate line bow phenomenon. Background technique [0004] A semiconductor device includes a cell region and a peripheral region. The cell area includes a plurality of memory cells for storing data, and the peripheral area includes different functional modules for programming, reading, and otherwise controlling the memory cells. Here, the peripheral region may include not only low-voltage transistors but also high-voltage transistors for supplying a high voltage. In the case of an ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/8247
CPCH01L27/11519H01L27/11524H10B41/10H10B41/35H10B41/42
Inventor 权贤律
Owner SK HYNIX INC