Method for forming PMOS (P-channel metal oxide semiconductor) transistor

Abstract

A method for forming a PMOS (P-channel metal oxide semiconductor) transistor includes the steps: providing a silicon substrate with formed isolating structures, wherein a portion of the silicon substrate among the isolating structures is provided with a gate structure; etching the gate structure on two sides of the silicon substrate and forming grooves on two sides of the gate structure to expose side walls of the isolating structures; passivating the silicon substrate and the isolating structures exposed from the grooves with gas containing halogen elements; and filling the grooves with germanium silicon materials. By the aid of the method, the problem of rolloff can be avoided, junction leakage current can be lowered, and the performance of the transistor is improved.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for forming a PMOS transistor. Background technique [0002] Since stress can change the energy gap and carrier mobility of silicon materials, improving the performance of MOS transistors through stress has become an increasingly common method. By properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, and the driving current can also be increased. Therefore, stress can greatly improve the performance of MOS transistors. [0003] In the prior art, the dual stress liner technology forms a tensile stress liner (tensile stress liner) on the NMOS transistor, and a compressive stress liner (compressive stress liner) on the PMOS transistor, thereby increasing the size of the PMOS transistor and the NMOS transistor. The driving current improves the response speed of the circuit. Accordin...

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Problems solved by technology

[0010] Due to the high activity of metal nickel, it is easy to diffuse into the junction 14a of the silicon germanium material 13 and the isolation structure 11, forming a "piping", and the piping is located at the junction of the source region and the drain region and the isolation structure 11 , will lead to a large junction leakage current (junction leakage) of the PMOS transistor, which will affect the performance of the device

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