A method and device for rate matching

Abstract

The invention discloses a method for rate matching, which is used for reducing time delay, saving hardware resources and improving rate matching efficiency. The method includes: firstly, inputting data of each way in multi-way data into a sub-matrix of an interleaved matrix; secondly, changing interleaving of at least one sub-matrix after the data are inputted, wherein the number of the sub-matrixes subjected to interleaving change is smaller than the amount of the sub-matrixes; thirdly, determining storage address relation of data in the sub-matrixes after interleaving change; fourthly, storing data in all sub-matrixes according to the determined storage address relation; and sixthly, reading the stored data according to parameter sequences to acquire data inputted after interleaving change. The invention further discloses a device for implementing the method.

Description

technical field [0001] The present invention relates to the communication field, in particular to a rate matching method and device. Background technique [0002] In a mobile communication system, some verification information is added to the data transmitted by the sending end in the channel after channel coding, and the decoding efficiency can be improved at the receiving end according to the verification information. In order to improve transmission efficiency, the sender needs to selectively process the verification information added in the encoding stage according to the current quality of the channel. This process is the process of rate matching. [0003] In the prior art, rate matching adopts a circular buffer rate matching method, and the algorithm includes three parts: bit interleaving, bit collection and bit clipping. For the process of bit interleaving, in the current hardware implementation technology, most of them are implemented serially according to the proto...

AI Technical Summary

Problems solved by technology

In the LTE (Long Term Evolution, long-term evolution) system, the data traffic is very large, and the processing time left for rate matching is very short. If serial implementation is adopted, the data is input in sequence, and then interleaved in sequence, and the delay will be It is very large and cannot meet the requirements of high throughput; and if multiple sets of circuits are implemented in parallel, multiple data can be input at the same time, and then the multi-channel input data can be interleaved together. Due to the large amount of data, the address calculation unit needed It is also relatively large, which will take up a lot of hardware resources, and in most cases, a multiplier is required to complete the calculation process, thereby increasing the cost of the hardware

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