Method and apparatus for testing joint test action group (JTAG) of memories

Abstract

The invention provides a method and an apparatus for testing JTAG of two types of memories. The invention which aims at the memories without JTAG test base pins uses chips on a single board and with the JTAG test base pins to realize the test without clamping the memories between the two chips with the JTAG test base pins. The method has the advantages of no need of many auxiliary devices, and realization of simplicity, rapidness and effectiveness.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a joint test action group (JTAG) testing method and device for memory. Background technique [0002] With the substantial increase in the chip density and scale of communication single boards and the sharp increase in the complexity of board wiring, the production of communication single boards faces a lot of testing and verification work. However, the traditional low-coverage automatic testing methods are increasingly difficult to ensure a high rate of one-time test pass rate for new boards. The remaining parts that have not been automatically tested need to use other methods to manually test and locate problems, which poses severe challenges to the construction period and manpower investment. . Therefore, how to make full use of automatic testing methods to improve the coverage of communication single-board production testing is a subject that needs to be taken seriously. [...

AI Technical Summary

Problems solved by technology

[0006] First, sandwich the chip without JTAG test pins between two chips with JTAG test pins. When the test data is sent and received between the two chips with JTAG test pins, it will pass through pin chip, which can indirectly test the continuity of the chip without JTAG test pins and the connection, but the memory chip is not suitable for being sandwiched between two chips with JTAG test pins, and the timing is difficult to meet;

[0007] Second, connect all pins of the chip without JTAG test pins to a programmable logic device, and then send the JTAG test waveform to each pin of the chip without JTAG test pins through this programmable logic device , and use an oscilloscope to observe the waveform at each pin one by one to judge whether the connection is on or off, but this method will occupy a large number of programmable logic device pins, and also requires a large number of auxiliary instruments, and can only judge whether the connection is on or off. Can not test the internal problems of the chip

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