Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Memory interface access control method and device

A memory access and interface control technology, applied in memory systems, instruments, memory address/allocation/relocation, etc., can solve the problem of low effective bandwidth of DDRX, achieve the effect of improving overall performance, improving access efficiency, and increasing throughput bandwidth

Active Publication Date: 2014-11-05
ZTE CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in existing applications, the effective bandwidth of DDRX is very low. No matter how high the rate of the interface is, the actual utilization rate of bandwidth resources is only about one-tenth.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Memory interface access control method and device
  • Memory interface access control method and device
  • Memory interface access control method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] The memory interface access control device provided by the embodiment of the present invention is set between the data storage application layer and the DDRX interface controller, the read and write instructions are sent from the data storage application layer as required, and the DDRX interface controls the access interface that converts the read and write instructions into DDRX . After the device of the invention processes the read and write instructions issued by the data storage application layer, the processed read and write instructions are sent to the DDRX interface controller.

[0059] like figure 2 As shown, the memory interface access control device according to the embodiment of the present invention mainly includes three parts: an address controller, an instruction queue, and a queue scanner.

[0060] The address controller is mainly used to remap the addresses in the read and write instructions sent by the data storage application layer. The specific map...

Embodiment 2

[0078] Figure 4 A DDRII device is shown as an example to describe an embodiment of this patent. The storage access of the application layer initiates read and write requests through three sets of signals, including: write command signal composed of wr_en, cmd, wr_data, wr_addr; read command signal composed of rd_en, cmd, rd_addr; read data valid indication composed of rd_data and data_valid Signal. The write command signal and the read command signal pass through the corresponding wr_cmd_fifo and rd_cmd_fifo to guide the access command flow of the application layer, which is convenient for the command controller to schedule.

[0079] The access address processed by cmd_fifo needs to be mapped. Its function is to map the address table in the application layer to different BANKs in the DDRII memory, so that the accessed data is evenly mapped in 8 different BANKs. The mapped address and the corresponding command are combined into an access command field, which is imported into...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Disclosed are a control method and device of a memory access interface. The device comprises an address controller, an instruction queue and an instruction queue scanner that are connected sequentially. The address controller is connected with a data storage application layer, and the instruction queue scanner is connected with an interface controller of a memory. The address controller is set so that: an instruction sent by the data storage application layer is mapped to difference spaces of the memory respectively, and read / write instructions of the different spaces are sent to corresponding instruction queues. The instruction queue is set to cache the received read / write instruction. The queue scanner is set to sequentially read the read / write instruction from each instruction queue, and send the read / write instruction to the interface controller of the memory. The present invention is capable of effectively improving the throughput bandwidth of a DDRX memory, achieving the same effect for a read operation and a write operation, and improving the access efficiency of the memory, thereby improving the overall performance of the device.

Description

technical field [0001] The present invention relates to the technical field of DDR (Double Data Rate, double-rate synchronous dynamic random access memory), and more specifically, to a memory interface access method and device. Background technique [0002] DDRX type memory is widely used in various communication devices, including DDR, DDRII and DDRIII, which use double-rate data bus memory. Compared with SSRAM (Synchronous Static Random Access Memory, Synchronous Static Random Access Memory), it stores High density (up to 1Gbit for a single particle), high interface rate (up to 1.333Ghz), low cost, and other advantages make it one of the most important devices in memory. [0003] In order to achieve the above-mentioned excellent characteristics, a lot of price must be paid in the design of the device. In order to achieve the index of larger storage capacity on a single chip, it is necessary to use as few transistors as possible in each storage unit (SSRAM requires at leas...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16G06F12/02
CPCG06F12/00G06F13/16G06F13/1668
Inventor 黄科
Owner ZTE CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com