Semiconductor memory, interface circuit and access method thereof
An access method and interface circuit technology, which is applied in the field of storage system and memory, can solve the problems that are not conducive to reducing the circuit area of the storage system, increasing the cost of the flash memory controller, and being inconvenient to expand the capacity of the storage system, etc.
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[0042] Figure 4A is a schematic diagram of a NAND flash memory according to a first embodiment of the present invention. The flash die 401 includes a die portion 406 , an interface circuit 410 consistent with prior art NAND flash dies. The interface circuit 410 includes a logic circuit 402 , a logic circuit 403 , a latch or flip-flop 404 , and a gate circuit 407 . Interface circuit 410 may be integrated on the same die as die portion 406, or provided in a separate die or chip.
[0043] The logic circuit 402 receives the address latch (ALE) signal, the command latch (CLE) signal and is connected to the address latch input (ALE_IN), command latch input (CLE_IN) ports of the die portion 406 . The logic circuit 402 also outputs an enable signal (CE_EN) to the gate circuit 407 . The gate circuit 407 receives the CE_EN signal and the write enable WE# / CLK signal from the logic circuit 402 . The output of gate circuit 407 is connected to the enable signal (G) input of latch or fl...
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