Parallel Viterbi decoder, decoding method and receiver
A Viterbi decoder and Viterbi decoding technology, applied in the field of communication, can solve the problems of not being able to provide bit rate, consume chip space, etc., achieve the effect of reducing the number, breaking through the threshold, and improving decoding efficiency
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[0048]This embodiment provides a parallel Viterbi decoding method, which uses final state information transfer to improve efficiency. By improving efficiency, it is possible to reduce the footprint and / or increase the throughput at data rates within a given thermal budget. In some embodiments, a decoder chip uses multiple decoders to operate a group of overlapping data blocks in parallel, and obtain a sequence of state metrics through addition and comparison operation, and these state metrics represent the most probable paths to each state . Each decoder communicates the final state information of the decoder selection for processing the preceding data block. Each decoder will sequentially receive final state information selected by a decoder that processes subsequent data blocks. The final state information eliminates the need for subsequent data block processing, thereby shortening the decoding process.
[0049] The present invention can be fully understood in conjunction...
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