IDMA (interleave division multiple access) bus bridge device

Abstract

The invention provides an IDMA bus bridge device which is used for performing reading-writing operation to a slave device supporting an IDMA interface by at least one primary device supporting a non-IDMA interface, wherein an IDMA signal generator is provided between the non-IDMA interface and the IDMA interface; the IDMA signal generator is provided with a control / state, address, write data and read data register; wherein, the reading / writing requirement position, the state position of the IDMA signal generator and the response position of the slave device are defined in the control / state register; the state position represents that the IDMA signal generator is in the current state of the performing process; the IDMA signal generator produces corresponding action at each state; the corresponding relationship among various states, different transfer conditions and the action of the IDMA signal generator at each state is defined; the primary device reads and writes four registers according to the defined state transfer order so as to complete the reading-writing operation of the slave device. According to the IDMA bus bridge device, the operation order of the primary device for four registers is improved to shorten the conversion period and improve operation efficiency.

Description

technical field [0001] The invention relates to an IDMA bus bridge device, in particular to an IDMA bus bridge device for implementing at least one master device supporting a non-IDMA interface to perform read and write operations on a slave device supporting an IDMA interface. Background technique [0002] The IDMA interface is a parallel I / O interface, through which an off-chip device supporting the IDMA interface can read and write to an on-chip device supporting the IDMA interface. [0003] IDMA read operation protocol such as Figure 6A As shown, the IDMA read operation can be divided into an address latch process and a data read process. [0004] During the address latch process, the off-chip device pulls down the chip select signal of the desired on-chip device, puts the desired address on the data input signal line, and then sends the address latch on the address latch signal line Signal. When the chip select signal of the on-chip device is pulled low, it means tha...

AI Technical Summary

Problems solved by technology

[0012] From the above two examples of read and write operations, it can be known that the application of the above improved scheme retains the integrity of the original IP, but whether it is a read operation or a write operation, the IDMA signal generator of the master device and the bus bridge is working in serial. There is a situation of waiting for each other, that is, when the master device is working, the IDMA signal generator is waiting; and when the IDMA signal generator is working, the master device is waiting, so it takes too much operating time

In addition, in the above scheme, because the initial value of the control / status register is 0x0, which is exactly the same as the value of the read request bit, if at the beginning, the master device writes data into the address register due to a mistake, it may cause an error. expected read operation, which leads to a series of problems

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