Flash memory control method based on command descriptors
A command descriptor, flash memory control technology, applied in electrical digital data processing, instruments, input/output to record carriers, etc., can solve problems such as increasing the burden on the host, many instructions, and large hardware decoding circuit area.
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[0029] Refer to the attached figure 2 , the figure describes a hardware structural block diagram of a single-channel flash controller based on the command descriptor-based flash memory control method of the present invention, supports 8-port flash memory interface, and the command descriptor written by the host computer or CPU exists in the system RAM . In the picture:
[0030] AHB (Advanced High performance Bus, system bus) host port: used for the flash memory controller to read and write data to the SOC (System on Chip, system on chip) chip system through the system bus.
[0031] AHB slave port: AHB bus device end, connected with non-flash memory controller, used for CPU to read and write flash memory controller through system bus.
[0032] Bus decoding module: connect to the AHB slave port, decode the AHB bus request, and send the read and write requests to the corresponding lower devices connected to it, such as figure 2 Register Bank, Descriptor Control Block, and Us...
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