Preparation method of transistor

Abstract

The invention discloses a preparation method of a transistor in the field of semiconductor manufacturing. The preparation method comprises the following steps of: providing a semiconductor substrate and forming a dummy gate structure on the semiconductor substrate; selectively etching the upper surface of the semiconductor substrate, wherein the thickness of the removed upper surface of the semiconductor substrate is first thickness; and forming a light doped source / drain region with the thickness being the first thickness on the upper surface of the semiconductor substrate by using a selective epitaxial growth method. The light doped source / drain region is formed by using an epitaxial growth method after etching, thus, the junction depth of the transistor is very small, the activation rate of doping ions in the light doped source / drain region can also be increased, and finally, the performance of the transistor is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a transistor. Background technique [0002] On the one hand, with the rapid development of Ultra Large Scale Integration (ULSI), the manufacturing process of integrated circuits has become more and more complex and refined. In order to improve integration and reduce manufacturing costs, the critical dimensions of semiconductor devices continue to decrease, and the number of semiconductor devices per unit area of ​​a chip continues to increase. While the critical dimensions of semiconductor devices are reduced, the patterns of semiconductor devices are also continuously miniaturized. For MOS transistors, when the channel length L of the MOS transistor is shortened to the sum of the source and drain depletion layer widths (W s +W d ) is compared, the device will deviate from the behavior of the long channel, that is, the channel length L approache...

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Problems solved by technology

[0004] On the other hand, in a semiconductor device using a polysilicon gate, a polysilicate gate, etc. as a gate, the polysilicon gate has the following problems: the effective thickness of the gate insulating film increases due to the gate loss phenomenon, and the The phenomenon of dopant permeating from P+ or N+ polysilicon gate to the substrate and the change of threshold voltage caused by the change of dopant distribution, etc.

Using the existing polysilicon gate also has the problem of being unable to achieve a low resistance value on a line with a very small width.

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