Semiconductor memory

Abstract

The invention relates to a semiconductor memory, comprising: - bit lines, - a memory cell array and, - at least one pair of sense amplifier banks, wherein each sense amplifier is connected to a corresponding bit line according to an interleaved arrangement resulting in interconnect spaces available in each sense amplifier bank of the pair parallel to the bit lines, characterized in that each sense amplifier bank further comprises at least one local column decoder for selecting at least one sense amplifier of the sense amplifier bank, the local column decoder being coupled to the at least one sense amplifier of the sense amplifier bank by means of an output line running in an available interconnect space parallel to the bit lines.

Description

technical field [0001] The present invention relates generally to semiconductor memories, and more particularly to dynamic random access memories (DRAMs) in which local column decoders are associated with interleaved sense amplifiers. Background technique [0002] Basically, DRAM is an integrated circuit that stores data in binary form (such as "1" or "0") in a large number of cells. The data is stored in the cell as a charge on a capacitor located in the cell. Typically, a high logic level is approximately equal to the supply voltage and a low logic level is approximately equal to ground. [0003] The cells of conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes word lines interconnecting the cells on that row with common control signals. Similarly, each column includes bit lines coupled to at most one cell in each row. Thus, word lines and bit line...

AI Technical Summary

Problems solved by technology

therefore figure 2 The structure also has the disadvantage of a large number of column address buses

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