Readout circuit of SRAM (Static Random Access Memory)

Abstract

The invention discloses a readout circuit of an SRAM (Static Random Access Memory), which comprises an amplifying circuit module, a clamping circuit module, a push-pull circuit module, a selection output circuit module and an output circuit module, wherein the amplifying circuit module is used for amplifying and outputting data in an SRAM array block and comprises a sense amplifier, the SA input end of the sense amplifier is connected with a sense amplifier enable control signal and a sense amplifier selection signal, and drain electrodes of a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube in which two SA output ends are located are respectively and commonly connected to a first output contact and a second output contact; the clamping circuit module is used for stretching the potential of the first output contact and the potential of the second output contact to low level before effective signals arrives; and the push-pull circuit module is used for performing adverse treatment on the potential of the first output contact and the potential of the second output contact and then selectively outputting the potential. The readout circuit of the SRAM improves the reading speed and the stability of a circuit and reduces the layout area of the circuit.

Description

technical field [0001] The present invention relates to a static random access memory (SRAM) cell circuit, and more particularly to a readout circuit for reading data in an SRAM storage cell. Background technique [0002] As an important type of semiconductor memory, SRAM has high transmission speed and low power consumption, so it is widely used in various integrated circuits. On the whole, the SRAM cell includes two parts, a cell array and a peripheral circuit. The cell array is the core of the SRAM cell, which is formed by SRAM memory cells arranged in rows and columns; and the peripheral circuit includes an input and output circuit, a timing generation circuit, and a row translator. A code circuit and an amplifying readout circuit, etc., where the amplifying readout circuit samples and amplifies the stored data in the designated unit, and transmits it to the output buffer. [0003] like figure 1 Shown is an existing SRAM readout circuit, which includes a plurality of m...

AI Technical Summary

Problems solved by technology

[0006] However, this circuit structure makes the wiring of a single output circuit complex, increases the layout area, and the circuit still has data read output competition at C, which also reduces the readout speed of the circuit and the stability of the circuit

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