Method for realizing parallel Turbo code interweaver and used in LTE (Long Term Evolution)

Abstract

The invention provides a method for realizing a parallel Turbo code interweaver and used in LTE (Long Term Evolution). The method comprises the following steps: establishing a recursion relationship expression which is adaptive to FPGA (Field Programmable Gate Array) and is output by an interweaver; establishing an auxiliary recursion relationship expression; establishing an initial value recursion relationship expression and an auxiliary relationship expression thereof; establishing a data splitting and combination mode which is convenient to calculate a mold to a K value; establishing an interweaving constant table; establishing corresponding relationship of a code block length and an interweaving constant table address; and realizing the parallel LTETurbo code interweaver in the FPGA. The interweaver accomplishes the output of eight interweaving addresses within one clock period; the eight addresses respectively read eight RAM (Random-Access Memory) with same content; a main control module is adopted to process so as to obtain eight bit data outputs; the calculation complexity of an existing parallel interweaver is reduced; the efficiency is eight times higher than that of a traditional 10bit interweaver; and the method has an extremely high commercial value in an LTE communication system.

Description

technical field [0001] The present invention belongs to the technical field of mobile communication and encoding, in particular relates to the long-term evolution technology (LTE for short) of the third-generation mobile communication technology, and belongs to the category of Turbo encoding technology. Background technique [0002] Turbo code is currently recognized as one of the best forward error correction codes, and is recognized by 3GPP LTE (3 rd Generation Partnership Project Long Term Evolution, the third generation partnership project long-term evolution) TS36.212 protocol adopted, the Turbo encoder structure is as follows figure 1 As shown, it consists of two component code encoders and an intra-code interleaver, where the intra-code interleaver plays a key role in Turbo codes and directly affects the decoding performance of Turbo codes. LTE uses a quadratic permutation polynomial (QPP) interleaver, which has the characteristic of "maximum contention-free". Accord...

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Problems solved by technology

The design of the parallel interleaver has greater flexibility. At present, the existing parallel interleaver has a complicated interleaving operation process for certain code block lengths. The operability is not strong, the number of clocks is uncertain in the process of interleaving modulo, and as the length of the code block increases, the number of clocks increases sharply, and the performance deteriorates sharply. This is the opposite of the original intention of shortening the encoding time of large code blocks. Compared with the serial interleaver, there is no substantive improvement in the FPGA implementation. The present invention starts with algorithm optimization and combines the characteristics of the FPGA device to propose a solution for the interleaver. This program greatly reduces the cost of the existing parallel interleaver. Computational complexity, which solves the bottleneck problem of downlink service channel coding efficiency

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