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Address scheduling method, device and system

A scheduling device and scheduling system technology, applied in the computer field, can solve the problem of low data access efficiency, and achieve the effects of improving data access efficiency and increasing address supply rate

Active Publication Date: 2015-05-27
泰州市海通资产管理有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In this way, a returned address needs to be rewritten into the supply address fifo (first in first out) memory, and it needs to wait for all the previous addresses in the address memory to be read out, which takes a long time, resulting in Data access is not efficient

Method used

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  • Address scheduling method, device and system
  • Address scheduling method, device and system
  • Address scheduling method, device and system

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Embodiment Construction

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0025] refer to figure 1 The structure diagram of the address scheduling in the provided message cache can be realized by FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), and applied to the hardware architecture based on FPGA and CPU shared memory DDR, such as using PCIe (X86 A bus structure for interconnecting the system and external devices) The bus establishes a connection between the X86CPU and the FPGA so that the FPGA and the X86CPU s...

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PUM

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Abstract

The embodiment of the invention provides an address scheduling method, an address scheduling device and an address scheduling system, relates to the field of computer information data processing, can improve an address supply rate, and further improve data access efficiency of equipment. The method is applied to the address scheduling system, the address scheduling system comprises the address scheduling device, a recycling address memory, a supply address memory and an address memory, and the recycling address memory, the supply address memory and the address memory are connected with the address scheduling device. The method comprises the following steps that: the address scheduling device reads an address from the recycling address memory in a preset time period; and the address is written into the supply address memory, wherein the address which is written into the supply address memory is used for message storage. The embodiment of the invention is applied to address scheduling.

Description

technical field [0001] The present invention relates to the field of computers, in particular to an address scheduling method, device and system. Background technique [0002] In the Internet IP system, a large amount of memory is used for packet caching, such as figure 1 As shown, the processing of cached messages is often only concentrated on some fields of the message. The common practice is to construct a PD (Packet Descriptor, Packet Descriptor (PD)) to replace the message, and the MAC (Medium Key information such as Access Control (media access control layer) address, media access control layer IP address, address and length of message storage is written into PD, and the address of message storage needs to be managed. When a message is input from the outside of the system, it needs to be stored When entering the memory, the system applies for an address, and the address dispatching system is responsible for outputting an address. The message is written according to th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L29/12
Inventor 雷春贾俊平马爽
Owner 泰州市海通资产管理有限公司