Address scheduling method, device and system
A scheduling device and scheduling system technology, applied in the computer field, can solve the problem of low data access efficiency, and achieve the effects of improving data access efficiency and increasing address supply rate
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[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0025] refer to figure 1 The structure diagram of the address scheduling in the provided message cache can be realized by FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), and applied to the hardware architecture based on FPGA and CPU shared memory DDR, such as using PCIe (X86 A bus structure for interconnecting the system and external devices) The bus establishes a connection between the X86CPU and the FPGA so that the FPGA and the X86CPU s...
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