Control Clock Input Buffer

Abstract

An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

Description

technical field [0001] The present invention relates generally to clock input buffers. Background technique [0002] Typically, clock input buffers are used to control inputs to various circuits. For example, in combination with low power double data rate 2 (LPDDR2) synchronous dynamic random access memory (LPDDR2-S (SDRAM)) or nonvolatile memory (LPDDR2-N), the clock enable (CKE) input signal can be used to stop Input buffers for all signals except clocks. The clock input buffer consumes power even when the clock is stable because the clock input buffer is implemented using a differential amplifier. Contents of the invention Description of drawings [0003] figure 1 is a schematic circuit diagram of an embodiment; [0004] figure 2 is a more detailed schematic circuit diagram of an embodiment of the present invention; [0005] image 3 a is a timing diagram of a clock enable signal according to one embodiment; [0006] image 3 b is a timing diagram of clock a...

AI Technical Summary

Problems solved by technology

The clock input buffer consumes power even when the clock is stable because the clock input buffer is implemented using a differential amplifier

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