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Method for manufacturing semiconductor integrated circuit

A manufacturing method and integrated circuit technology, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as incomplete etching, and achieve the effect of improving reliability and reducing the possibility of disconnection

Active Publication Date: 2012-12-12
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the present invention hereby provides a method for manufacturing a semiconductor integrated circuit to solve the problems of incomplete etching caused by particles adhering to the metal hard mask.

Method used

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  • Method for manufacturing semiconductor integrated circuit
  • Method for manufacturing semiconductor integrated circuit
  • Method for manufacturing semiconductor integrated circuit

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Embodiment Construction

[0019] see Figure 1 to Figure 6 , Figure 1 to Figure 6 It is a schematic diagram of a preferred embodiment of the manufacturing method of the semiconductor integrated circuit provided by the present invention. Such as figure 1 As shown, this preferred embodiment first provides a substrate 100, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc., and the substrate 100 includes a conductive layer 102 and a layer covering the conductive layer 102. Ground floor 104. In the preferred embodiment, the conductive layer 102 includes a metal material, and the bottom layer 104 includes nitrogen-doped silicon carbide. In addition, the substrate 100 further includes a dielectric layer 106, and as figure 1 As shown, a dielectric layer 106 covers the bottom layer 104 . The dielectric layer 106 may include low dielectric constant (dielectric constant, k) material (dielectric constant value less than 3.9), ultra low dielectric con...

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Abstract

The invention discloses a method for manufacturing a semiconductor integrated circuit. The method comprises the steps of firstly, providing a substrate, and forming at least one metal hard mask on the substrate; and conducting a patterning step on metal hard masks, patterning metal hard masks to form patterned metal hard masks, and then conducting water plasma treatment on patterned metal hard masks.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a semiconductor integrated circuit using a metal hard mask. Background technique [0002] In the current semiconductor industry, damascene technology has been the main technology for multi-level interconnects in semiconductor integrated circuits. The damascene technology can be briefly described as firstly etching a circuit pattern in a dielectric material layer, and then filling the circuit pattern with a conductive material such as copper, and then planarizing it, and then completing the fabrication of the metal interconnection. According to the way of etching patterns in the dielectric material layer, damascene technology can be subdivided into trench-first (trench-first) process, via-first (via-first), partial-via-first (partial-via) process -first) process, and self-aligned (self-aligned) process. [0003] In the kn...

Claims

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Application Information

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IPC IPC(8): H01L21/768
Inventor 陈俊隆
Owner UNITED MICROELECTRONICS CORP
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