Clock generation circuit for successive approximation AD converter

Abstract

A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.

Description

technical field [0001] The present invention relates to a clock generating circuit, and more specifically, to a circuit for generating a sampling clock and an internal clock used in a successive approximation AD converter. Background technique [0002] At present, it is realized as an AD conversion with a relatively simple circuit configuration, and has a high degree of integration with a CMOS process that can be manufactured relatively cheaply, and can achieve a medium conversion speed and a medium conversion accuracy. A successive approximation type AD converter is known (for example, Non-Patent Document 1, etc.). [0003] Figure 15 A configuration example of a successive approximation AD converter is shown. This successive approximation AD converter converts an analog signal Vin into a 4-bit digital signal, and includes a capacitive DA converter 91 and a differential latch comparator 92 . The capacitive DA converter 91 includes capacitors 901 to 904 , a sampling switch...

AI Technical Summary

Problems solved by technology

If the low-level period of the internal clock becomes too long, the pulse of the internal clock (high-level period) cannot be accommodated in the low-level period of the sampling clock. As a result, there is a successive approximation AD Possibility of inverter malfunction

Also, when the low-level period of the internal clock is shorter than the charge redistribution time, there is a possibility that the charge redistribution process cannot be completed during the low-level period of the internal clock.

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