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Wafer-level chip-scale package with reduced stress on solder balls

A Young's modulus, metal pad technology, applied in the field of wafer-level chip-scale packaging, can solve problems such as substandard packaging, the die cannot be replaced with a good die, the die cannot be removed, etc.

Active Publication Date: 2015-08-19
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The reason is that if the underfill is applied, the bond between the die and the PCB is irreparable and if the die is defective, the die can no longer be removed from the respective PCB
Therefore, if underfill is applied, once bonded, the defective die cannot be replaced with a good die, causing the entire package to fail

Method used

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  • Wafer-level chip-scale package with reduced stress on solder balls
  • Wafer-level chip-scale package with reduced stress on solder balls
  • Wafer-level chip-scale package with reduced stress on solder balls

Examples

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Embodiment Construction

[0029] The making and using of embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the disclosed embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative only, and do not limit the scope of the disclosure.

[0030] According to an embodiment a wafer level chip scale package (WLCSP) is provided. Intermediate stages in the manufacture of various embodiments are illustrated. Variations of the examples are discussed. Throughout the various views and exemplary embodiments, the same reference numerals are used to designate the same elements.

[0031] figure 1 An exemplary die 100 is shown, which is a WLCSP according to an embodiment. Die 100 may include substrate 20, which may be a semiconductor substrate, such as a silicon substrate, but which may also include other semiconductor materials such as silicon german...

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Abstract

A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a wafer-level chip-scale package. Background technique [0002] In the formation of a wafer level chip scale package (WLCSP), integrated circuit devices such as transistors are first formed on the surface of a semiconductor substrate in a wafer. An interconnect structure is then formed over the integrated circuit device. A metal pad is formed over the interconnect structure and electrically connected to the interconnect structure. A passivation layer and a first polyimide layer are formed on the metal pad, and the metal pad is exposed through openings in the passivation layer and the first polyimide layer. [0003] A post passivation interconnect (PPI) is then formed, followed by a second polyimide layer formed over the PPI. An under bump metallurgy (UBM) is formed extending into the opening in the second polyimide layer, wherein the UBM is electrically connected to the PPL. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L23/31G03F7/075G03F7/004
CPCH01L24/05H01L24/13H01L2224/0401H01L2224/05572H01L23/293H01L2224/05022H01L23/3114H01L23/562H01L2924/00014H01L23/3192H01L2224/05008H01L2224/05569H01L2224/131H01L2924/014H01L2224/05552
Inventor 陈玉芬蔡侑伶普翰屏郭宏瑞黄毓毅
Owner TAIWAN SEMICON MFG CO LTD