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Programmable keeper for semiconductor memories

A memory and semiconductor technology that is used in static memory, read-only memory, digital memory information, etc., and can solve problems such as high DC leakage current, increased power consumption, and limited VCCmin operation.

Active Publication Date: 2013-01-30
TAIWAN SEMICON MFG CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these conventional keeper circuits may also have high DC leakage currents, especially during low voltage operation, and result in slower operating times for semiconductor memories
In addition, this traditional keeper is designed for worst-case coding, which can limit VCCmin operation and further increase power consumption

Method used

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  • Programmable keeper for semiconductor memories
  • Programmable keeper for semiconductor memories
  • Programmable keeper for semiconductor memories

Examples

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Embodiment Construction

[0026] Preferably, the disclosed semiconductor memories and methods of designing and manufacturing semiconductor memories provide keeper circuits with dimensions optimized for the type of bitcell connected to a particular bitline, e.g., output logic during a read operation A bit cell of 1 or logic 0. A keeper circuit optimized for the type of bit cell connected to the bit line can reduce the power consumption of the semiconductor memory while improving the operating speed and low power, VCCmin operation of the semiconductor memory.

[0027] figure 1 An example of a modified read-only memory ("ROM") array 100 is shown that includes a plurality of programmed 0 bit cells 102 (i.e., bit cells configured to output logic 0) and a number of programmed 1-bit cells 104 (ie, the bit line is configured to output a logic 1 when read). Bit cells 102 and 104 are arranged in number of rows (n) and columns (m). Each bit cell 102, 104 located in a row is connected to a word line ("WL"), and...

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PUM

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Abstract

A method includes receiving a memory code identifying a number of logic zeroes and logic ones to be stored in a semiconductor memory, determining a number of bit cells of a first type that are to be coupled to a first bit line of the semiconductor memory from the memory code, and selecting a first keeper circuit from a plurality of keeper circuits based on the number of bit cells of the first type that are to be coupled to the first bit line. An electronic representation of a layout of the semiconductor memory is stored in a non-volatile machine readable storage medium. The invention further provides a programmable keeper for semiconductor memories

Description

technical field [0001] The disclosed systems and methods relate to semiconductor memory. More specifically, the disclosed systems and methods relate to programmable keeper for semiconductor memory. Background technique [0002] Semiconductor memories such as random access memory (“RAM”) and read only memory (“ROM”) may include keeper circuits connected to bit lines, thereby reducing leakage current and reducing noise, preventing damage to slave connections The data read from the memory bit cell to the bit line. However, these conventional keeper circuits may also have higher DC leakage currents, especially during low voltage operation, and result in slower operating times for semiconductor memories. Furthermore, such conventional keeper is designed for worst-case encoding, which may limit VCCmin operation and further increase power consumption. Contents of the invention [0003] In order to solve the problems existing in the prior art, according to one aspect of the pre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/12
CPCG11C7/02G11C7/12G06F30/34G11C17/12
Inventor 刘逸群
Owner TAIWAN SEMICON MFG CO LTD
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